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Matrix (AMX and ACE)

AMX-MOVRS

Tile loads with a read-shared hint, for data that many cores read.

CPUID
AMX_MOVRS
CPUID.(EAX=1EH,ECX=1):EAX[8]
Instructions
2 mnemonics
Processors
Diamond Rapids

AMX-MOVRS adds TILELOADDRS and TILELOADDRST1, tile loads with the read-shared hint of MOVRS: other cores are likely to read the same data before anyone writes it, as with the weights of a neural network that several threads multiply at once. The hint never changes the result. Intel lists Diamond Rapids as the first processor with it.

Instructions

Mnemonics with at least one form in AMX-MOVRS. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
TILELOADDRSLoads a tile from memory like TILELOADD, with a hint that other cores are likely to read the same data before it is written.1
TILELOADDRST1Loads a tile like TILELOADDRS, with the added hint that the data will be reused but need not stay in the nearest cache.1

CPUID and processors

XED splits AMX-MOVRS into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AMX-MOVRS. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AMX_MOVRS

AMX_MOVRS
CPUID.(EAX=1EH,ECX=1):EAX[8] AMX_MOVRS

Diamond Rapids

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.