Matrix (AMX and ACE)
AMX-TILE
The base of Advanced Matrix Extensions: eight tile registers of up to 1 KiB each, their configuration, and tile loads and stores.
- CPUID
- AMX_TILE
CPUID.(EAX=07H,ECX=0):EDX[24] - Instructions
- 7 mnemonics
- Processors
- Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
- Linux flag
amx_tile
AMX (Advanced Matrix Extensions) gives the processor a two-dimensional register file for matrix multiplication. AMX-TILE is the base: the registers, their configuration and the loads and stores. The arithmetic comes in separate extensions for each data type, starting with AMX-INT8 and AMX-BF16, which Sapphire Rapids introduced together with AMX-TILE.
Tiles
There are eight tile registers, tmm0 to tmm7. With palette 1, the only configuration defined for AMX so far, each tile holds up to 16 rows of 64 bytes, 1 KiB, and 8 KiB in all. Before use, a program describes the shape of each tile (its rows and bytes per row) in a 64-byte block and loads it with LDTILECFG. A matrix that does not fill a tile simply uses fewer rows or shorter rows.
- TILELOADD and TILESTORED move a tile between registers and memory, one row at a time, with the distance between rows given by the index register of the address. TILELOADDT1 adds a hint that the data need not stay in the nearest caches.
- TILEZERO clears a tile, typically an accumulator before a new block of the result.
- TILERELEASE returns all tile state to its initial, unconfigured state. State in that condition need not be saved: XSAVEC and XSAVES skip it (the init optimization), and so do Linux signal frames.
All AMX instructions exist only in 64-bit mode.
Operating system support
The tile state is managed with XSAVE: XCR0 bit 17 covers the 64-byte
configuration (TILECFG) and bit 18 the 8 KiB of tile data (TILEDATA).
Because 8 KiB would make every signal frame and thread much larger,
Linux does not give tile data to every process. A program first asks
for it with arch_prctl(ARCH_REQ_XCOMP_PERM, 18); a tile instruction
used without that permission raises SIGILL. The permission covers the
whole process, passes to children on fork and ends at exec.
Detection
AMX-TILE is CPUID.(EAX=07H,ECX=0):EDX[24]. Leaf 1DH describes the palettes and leaf 1EH the matrix unit; sub-leaf 1 of leaf 1EH repeats the AMX feature bits and adds those of newer AMX extensions. The ACE extensions of the x86 Ecosystem Advisory Group reuse this framework with a second palette.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| LDTILECFG | Loads the AMX tile configuration (palette, rows and bytes per row of each tile) from a 64-byte memory block and zeroes the tile registers. | 1 |
| STTILECFG | Stores the current AMX tile configuration to a 64-byte memory block. | 1 |
| TILELOADD | Loads a tile from memory, row by row, with the row stride taken from the index register of its SIB-encoded address. | 1 |
| TILELOADDT1 | Loads a tile like TILELOADD, with a hint that the data will be reused but need not stay in the nearest cache. | 1 |
| TILERELEASE | Returns the AMX tile configuration and all tile data to their initial state: unconfigured and zero. | 1 |
| TILESTORED | Stores a tile to memory, row by row, with the row stride taken from the index register of its SIB-encoded address. | 1 |
| TILEZERO | Sets every byte of a tile register to zero. | 1 |
CPUID and processors
XED splits AMX-TILE into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AMX_TILE | AMX_TILE | Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AMX_TILE_BASE | ACE v1 or AMX_TILE | Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
- Linux kernel documentation: Using XSTATE features in user space applications
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.