APX

APX is the largest change to the general-purpose side of x86-64 since AMD’s original 64-bit extension added R8 to R15. It gives 64-bit code twice as many integer registers and removes two long-standing constraints of the x86 integer instructions: that the destination is also a source, and that almost every arithmetic instruction overwrites the flags.

Sixteen more registers#

APX adds R16 to R31, the extended general-purpose registers (EGPRs). They exist only in 64-bit mode and behave like R8 to R15, but they are XSAVE-managed state: the operating system must set bit 19 of XCR0 before any APX instruction runs, and saves and restores them with XSAVE like vector registers. Their 128-byte save area reuses the space of the retired MPX state.

Two prefixes reach them:

• REX2 is a two-byte prefix, D5 followed by a payload byte. It carries the REX bits plus a fifth bit for each register number, and works with the instructions of legacy opcode maps 0 and 1, which covers most integer code. Opcode rows whose instructions name no register, such as the short Jcc row 7x, are reserved under REX2; the single exception, A1, becomes JMPABS.
• The extended EVEX prefix reuses reserved bits of EVEX for the high register bits. Integer instructions promoted from the legacy maps move to the new EVEX map 4; promoted VEX instructions such as ANDN or SHLX keep their maps. Existing EVEX vector instructions can use the new registers in their memory addresses.

Because REX2 is two bytes shorter than EVEX, it is the encoding of choice whenever an instruction only needs the extra registers.

New data destination (NDD)#

With EVEX.ND set, many integer instructions take an extra destination register, so ADD r10, r11, r12 computes r11 + r12 without destroying either source. The promoted instructions with NDD forms include ADD, SUB, AND, OR, XOR, ADC, SBB, INC, DEC, NEG, NOT, the shifts and rotates, IMUL and CMOVcc. An NDD destination is always written in full: results narrower than 64 bits are zero-extended, where the legacy 8- and 16-bit forms keep the upper bits. A few instructions without an NDD form, such as the immediate forms of IMUL and SETcc, use the same bit to zero the upper bits instead (ZU).

Flag suppression (NF)#

With EVEX.NF set, an instruction leaves the arithmetic flags as they were. The compiler can then schedule arithmetic between a compare and the branch or conditional move that consumes its flags. NF applies to the common arithmetic, logic, shift, multiply and divide instructions, to LZCNT, TZCNT and POPCNT, and to the promoted BMI instructions that write flags, such as ANDN and BZHI.

Conditional instructions#

APX makes if-conversion cheaper for the compiler:

• CCMPscc and CTESTscc compare or test only if a condition holds, and otherwise load the flags from a value in the instruction, so a == 1 && b == 2 needs one branch.
• CFCMOVcc is a conditional move that neither performs nor faults on its memory access when the condition is false, which lets a compiler turn a guarded load or store into straight-line code. With a register destination it writes zero when the condition is false.
• SETcc gains a zero-upper form that writes the whole register, removing the usual zeroing instruction before it.

The REX2 forms of CMOVcc keep the legacy behavior, memory faults included, so that their timing still follows Intel’s guidance for constant-time cryptographic code.

Saving registers#

More registers mean more to save around calls. PUSH2 and POP2 move two registers in one instruction to a 16-byte-aligned stack slot. The push-pop acceleration (PPX) hint, available on PUSHP, POPP, PUSH2P and POP2P, marks a push and the pop that reads it back, so the processor can forward the value without a round trip through memory. The hint never changes what the program does.

Detection#

APX_F is CPUID.(EAX=07H,ECX=1):EDX[21]. It also announces leaf 29H, whose EBX[0] (APX_NCI_NDD_NF) covers the new conditional instructions and the NDD and NF controls. Intel’s specification says every Intel processor with APX_F also sets that bit; XED keeps the forms that need it in a separate ISA set, APX_F_N3, that requires both. Software must also check that the operating system enabled XCR0 bit 19; without it every APX instruction and prefix raises #UD.

GCC 14 added part of APX (the extra registers, NDD, PPX and PUSH2/POP2) behind -mapxf. XED’s chip model places APX in Diamond Rapids and Nova Lake.

Instructions

CPUID and processors

XED splits APX into 31 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.