x86-64.net

Vector (SSE, AVX and AVX10)

AVX-IFMA

VEX-encoded multiply-add of 52-bit unsigned integers into 64-bit accumulators, a building block for big-number arithmetic.

CPUID
AVX_IFMA
CPUID.(EAX=07H,ECX=1):EAX[23]
Instructions
2 mnemonics
Processors
Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Sierra Forest, Clearwater Forest, Zen 6

AVX-IFMA brings the two 52-bit integer multiply-adds of AVX512_IFMA to VEX encoding. VPMADD52LUQ multiplies the low 52 bits of each pair of qwords, a 104-bit product, and adds the low 52 bits of that product to a 64-bit accumulator; VPMADD52HUQ adds the high 52 bits. The pair suits arithmetic on large integers split into 52-bit pieces, as in public-key cryptography: the 12 spare bits of each 64-bit accumulator leave room to add many partial products before carries must be propagated.

Instructions

Mnemonics with at least one form in AVX-IFMA. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
VPMADD52HUQMultiplies the low 52 bits of packed unsigned quadwords into 104-bit products and adds the high 52 bits of each product to a 64-bit accumulator.4
VPMADD52LUQMultiplies the low 52 bits of packed unsigned quadwords into 104-bit products and adds the low 52 bits of each product to a 64-bit accumulator.4

CPUID and processors

XED splits AVX-IFMA into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AVX-IFMA. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX_IFMA

AVX_IFMA
CPUID.(EAX=07H,ECX=1):EAX[23] AVX_IFMA

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Sierra Forest, Clearwater Forest, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.