CPUID
AVX_VNNI_INT16
CPUID.(EAX=07H,ECX=1):EDX[10]
Instructions
6 mnemonics
Processors
Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Clearwater Forest

AVX-VNNI-INT16 does for 16-bit integers what AVX-VNNI-INT8 does for bytes: dot products of pairs of words with every sign combination that VPDPWSSD lacks, namely VPDPWSUD, VPDPWUSD and VPDPWUUD, each with a saturating variant. The AVX10.2 specification names 16-bit video processing as a use. AVX10.2 adds EVEX forms.

Instructions

Mnemonics with at least one form in AVX-VNNI-INT16. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
VPDPWSUDMultiplies signed words of the first source by unsigned words of the second and adds each pair of products to a 32-bit accumulator.4
VPDPWSUDSMultiplies signed words of the first source by unsigned words of the second and adds each pair of products to a 32-bit accumulator, saturating.4
VPDPWUSDMultiplies unsigned words of the first source by signed words of the second and adds each pair of products to a 32-bit accumulator.4
VPDPWUSDSMultiplies unsigned words of the first source by signed words of the second and adds each pair of products to a 32-bit accumulator, saturating.4
VPDPWUUDMultiplies unsigned words by unsigned words and adds each pair of products to the matching 32-bit accumulator.4
VPDPWUUDSMultiplies unsigned words by unsigned words and adds each pair of products to the matching 32-bit accumulator with unsigned saturation.4

CPUID and processors

XED splits AVX-VNNI-INT16 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AVX-VNNI-INT16. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX_VNNI_INT16

AVX_VNNI_INT16
CPUID.(EAX=07H,ECX=1):EDX[10] AVX_VNNI_INT16

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Clearwater Forest

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.