AVX instruction set extension

AVX doubled the width of the vector registers: the 16 YMM registers hold 256 bits, and the XMM registers are their low halves. Its VEX prefix changed how vector instructions are written. They take three operands, so the destination need not be one of the sources, most memory operands need no alignment, and a VEX instruction that writes an XMM register clears the rest of the YMM register. Most SSE instructions have a VEX form with a V in front of their name, such as VADDPS, and the floating-point ones reach 256 bits; integer instructions stayed at 128 bits until AVX2.

Using AVX needs the operating system to save the YMM state: it enables it in XCR0, which programs check with XGETBV together with the OSXSAVE bit (see XSAVE). Mixing VEX and legacy SSE code without VZEROUPPER in between costs time on many processors. AVX is part of x86-64-v3.

Instructions

Mnemonics with at least one form in AVX. Each page lists all forms of the mnemonic, including those of other extensions.

Mnemonic	Summary	Forms
VADDPD	Adds packed doubles.	4
VADDPS	Adds packed singles.	4
VADDSD	Adds the low doubles; the other elements come from the first source.	2
VADDSS	Adds the low singles; the other elements come from the first source.	2
VADDSUBPD	Subtracts in the even-numbered doubles and adds in the odd-numbered ones of two XMM or YMM sources, into a separate destination.	4
VADDSUBPS	Subtracts in the even-numbered singles and adds in the odd-numbered ones of two XMM or YMM sources, into a separate destination.	4
VANDNPD	Computes the bitwise AND of the inverted first source with the second, as packed doubles.	4
VANDNPS	Computes the bitwise AND of the inverted first source with the second, as packed singles.	4
VANDPD	Computes the bitwise AND of packed doubles.	4
VANDPS	Computes the bitwise AND of packed singles.	4
VBLENDPD	Picks each double from the first or the second source, as a bit of an immediate says, into a separate XMM or YMM destination.	4
VBLENDPS	Picks each single from the first or the second source, as a bit of an immediate says, into a separate XMM or YMM destination.	4
VBLENDVPD	Picks each double from the first or the second source by the sign bit of the matching element of a fourth register operand.	4
VBLENDVPS	Picks each single from the first or the second source by the sign bit of the matching element of a fourth register operand.	4
VBROADCASTF128	Loads 128 bits of floating-point data from memory into both halves of a YMM register.	1
VBROADCASTSD	Copies one double from memory or an XMM register to every element of a vector.	1
VBROADCASTSS	Copies one single from memory or an XMM register to every element of a vector.	2
VCMPPD	Compares packed doubles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	4
VCMPPS	Compares packed singles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	4
VCMPSD	Compares the low doubles with one of 32 predicates an immediate selects, into an all-ones or zero element (VEX) or a mask register (EVEX).	2
VCMPSS	Compares the low singles with one of 32 predicates an immediate selects, into an all-ones or zero element (VEX) or a mask register (EVEX).	2
VCOMISD	Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception.	2
VCOMISS	Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception.	2
VCVTDQ2PD	Converts packed signed doublewords to doubles.	4
VCVTDQ2PS	Converts packed signed doublewords to singles.	4
VCVTPD2DQ	Converts packed doubles to signed doublewords, rounding as MXCSR or the instruction selects.	4
VCVTPD2PS	Converts packed doubles to singles, rounding as MXCSR or the instruction selects.	4
VCVTPS2DQ	Converts packed singles to signed doublewords, rounding as MXCSR or the instruction selects.	4
VCVTPS2PD	Converts packed singles to doubles, which is exact.	4
VCVTSD2SI	Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects.	4
VCVTSD2SS	Converts the low double of the second source to single, rounding as MXCSR or the instruction selects; the other elements come from the first source.	2
VCVTSI2SD	Converts a signed 32- or 64-bit integer to double in the low element; the other elements come from the first source.	4
VCVTSI2SS	Converts a signed 32- or 64-bit integer to single in the low element; the other elements come from the first source.	4
VCVTSS2SD	Converts the low single of the second source to double, which is exact; the other elements come from the first source.	2
VCVTSS2SI	Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects.	4
VCVTTPD2DQ	Converts packed doubles to signed doublewords, truncating toward zero.	4
VCVTTPS2DQ	Converts packed singles to signed doublewords, truncating toward zero.	4
VCVTTSD2SI	Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero.	4
VCVTTSS2SI	Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero.	4
VDIVPD	Divides packed doubles.	4
VDIVPS	Divides packed singles.	4
VDIVSD	Divides the low doubles; the other elements come from the first source.	2
VDIVSS	Divides the low singles; the other elements come from the first source.	2
VDPPD	Computes a dot product of two packed doubles, with an immediate choosing which products to add and where the sum goes.	2
VDPPS	Computes a dot product of the singles in each 128-bit lane, with an immediate choosing which products to add and where the sums go.	4
VEXTRACTF128	Copies the 128-bit half of a YMM register that an immediate selects to an XMM register or memory.	2
VEXTRACTPS	Copies the single that an immediate selects from an XMM register to a general-purpose register or memory.	2
VHADDPD	Adds the pair of doubles within each 128-bit lane of two sources, the first source's sums going to the even positions.	4
VHADDPS	Adds adjacent pairs of singles within each 128-bit lane of two sources, the first source's two sums going low in the lane.	4
VHSUBPD	Subtracts the high double from the low one within each 128-bit lane of two sources, the first source's results going to the even positions.	4
VHSUBPS	Subtracts the odd single from the even one in adjacent pairs within each 128-bit lane, the first source's results going low.	4
VINSERTF128	Copies the first source to a YMM register and replaces the half an immediate selects with 128 bits from an XMM register or memory.	2
VINSERTPS	Inserts a single from a register or memory into an XMM register at the position an immediate gives, and can zero other elements.	2
VLDDQU	Loads 128 or 256 unaligned bits like VMOVDQU, but may read more bytes around them, for loads that cross cache lines.	2
VLDMXCSR	Loads the MXCSR register, the SSE control and status bits, from memory; the VEX form of LDMXCSR.	1
VMASKMOVDQU	Stores the bytes of an XMM register whose mask byte has its top bit set to [RDI], non-temporally; the VEX form of MASKMOVDQU.	1
VMASKMOVPD	Loads or stores packed doubles only where the sign bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault.	4
VMASKMOVPS	Loads or stores packed singles only where the sign bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault.	4
VMAXPD	Returns the larger of each pair of packed doubles, or the second operand if either is NaN or both are zero.	4
VMAXPS	Returns the larger of each pair of packed singles, or the second operand if either is NaN or both are zero.	4
VMAXSD	Returns the larger of the low doubles, or the second operand if either is NaN or both are zero; the other elements come from the first source.	2
VMAXSS	Returns the larger of the low singles, or the second operand if either is NaN or both are zero; the other elements come from the first source.	2
VMINPD	Returns the smaller of each pair of packed doubles, or the second operand if either is NaN or both are zero.	4
VMINPS	Returns the smaller of each pair of packed singles, or the second operand if either is NaN or both are zero.	4
VMINSD	Returns the smaller of the low doubles, or the second operand if either is NaN or both are zero; the other elements come from the first source.	2
VMINSS	Returns the smaller of the low singles, or the second operand if either is NaN or both are zero; the other elements come from the first source.	2
VMOVAPD	Moves packed doubles between registers and memory that must be aligned to the vector size.	8
VMOVAPS	Moves packed singles between registers and memory that must be aligned to the vector size.	8
VMOVD	Moves 32 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form.	4
VMOVDDUP	Duplicates each even-numbered double into the next odd position.	4
VMOVDQA	Moves 128 or 256 bits of integer data between vector registers and memory, which must be aligned to the vector size.	8
VMOVDQU	Moves 128 or 256 bits of integer data between vector registers and memory without an alignment requirement.	8
VMOVHLPS	Moves the high two singles of the second source into the low half of the result, the high half coming from the first source.	1
VMOVHPD	Loads a double from memory into the high half of an XMM register, or stores the high double to memory.	2
VMOVHPS	Loads two singles from memory into the high half of an XMM register, or stores the high two to memory.	2
VMOVLHPS	Moves the low two singles of the second source into the high half of the result, the low half coming from the first source.	1
VMOVLPD	Loads a double from memory into the low half of an XMM register, or stores the low double to memory.	2
VMOVLPS	Loads two singles from memory into the low half of an XMM register, or stores the low two to memory.	2
VMOVMSKPD	Copies the sign bits of the packed doubles of an XMM or YMM register into the low bits of a general-purpose register.	2
VMOVMSKPS	Copies the sign bits of the packed singles of an XMM or YMM register into the low bits of a general-purpose register.	2
VMOVNTDQ	Stores an integer vector to aligned memory with a non-temporal hint that avoids polluting the caches.	2
VMOVNTDQA	Loads a vector from aligned memory with a non-temporal hint, which lets it read write-combining memory efficiently.	1
VMOVNTPD	Stores packed doubles to aligned memory with a non-temporal hint that avoids polluting the caches.	2
VMOVNTPS	Stores packed singles to aligned memory with a non-temporal hint that avoids polluting the caches.	2
VMOVQ	Moves a quadword between an XMM register and a general-purpose register, memory or another XMM register, zeroing the rest of a vector destination.	8
VMOVSD	Moves the low double between XMM registers or to and from memory; a load zeroes the rest of the register.	4
VMOVSHDUP	Duplicates each odd-numbered single into the even position below it.	4
VMOVSLDUP	Duplicates each even-numbered single into the odd position above it.	4
VMOVSS	Moves the low single between XMM registers or to and from memory; a load zeroes the rest of the register.	4
VMOVUPD	Moves packed doubles between registers and memory without an alignment requirement.	8
VMOVUPS	Moves packed singles between registers and memory without an alignment requirement.	8
VMPSADBW	Computes, per 128-bit lane, word sums of absolute differences between a 4-byte block of the second source and eight sliding blocks of the first.	2
VMULPD	Multiplies packed doubles.	4
VMULPS	Multiplies packed singles.	4
VMULSD	Multiplies the low doubles; the other elements come from the first source.	2
VMULSS	Multiplies the low singles; the other elements come from the first source.	2
VORPD	Computes the bitwise OR of packed doubles.	4
VORPS	Computes the bitwise OR of packed singles.	4
VPABSB	Computes the absolute value of packed signed bytes.	2
VPABSD	Computes the absolute value of packed signed doublewords.	2
VPABSW	Computes the absolute value of packed signed words.	2
VPACKSSDW	Narrows signed doublewords from two sources to words with signed saturation.	2
VPACKSSWB	Narrows signed words from two sources to bytes with signed saturation.	2
VPACKUSDW	Narrows signed doublewords from two sources to words with unsigned saturation.	2
VPACKUSWB	Narrows signed words from two sources to bytes with unsigned saturation.	2
VPADDB	Adds packed bytes, wrapping around on overflow.	2
VPADDD	Adds packed doublewords, wrapping around on overflow.	2
VPADDQ	Adds packed quadwords, wrapping around on overflow.	2
VPADDSB	Adds packed signed bytes with signed saturation.	2
VPADDSW	Adds packed signed words with signed saturation.	2
VPADDUSB	Adds packed unsigned bytes with unsigned saturation.	2
VPADDUSW	Adds packed unsigned words with unsigned saturation.	2
VPADDW	Adds packed words, wrapping around on overflow.	2
VPALIGNR	Concatenates two sources in each 128-bit lane and extracts 16 bytes starting at a byte offset given by an immediate.	2
VPAND	Computes the bitwise AND of two XMM or YMM sources into a separate destination (YMM with AVX2).	2
VPANDN	Computes the bitwise AND of the inverted first source with the second, in XMM or YMM registers (YMM with AVX2).	2
VPAVGB	Computes the rounded average of packed unsigned bytes.	2
VPAVGW	Computes the rounded average of packed unsigned words.	2
VPBLENDVB	Picks each byte from the first or the second source by the top bit of the matching byte of a fourth register operand.	2
VPBLENDW	Picks each word from the first or the second source by a bit of an immediate, the same eight bits for each 128-bit lane.	2
VPCLMULQDQ	Carry-less multiplies one quadword of each source, chosen by an immediate, into a 128-bit product in each 128-bit lane.	2
VPCMPEQB	Compares packed bytes for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPEQD	Compares packed doublewords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPEQQ	Compares packed quadwords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPEQW	Compares packed words for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPESTRI	Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with VEX.W1) as an immediate says, returning an index in ECX.	4
VPCMPESTRM	Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with VEX.W1) as an immediate says, returning a mask in XMM0.	4
VPCMPGTB	Tests packed signed bytes for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPGTD	Tests packed signed doublewords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPGTQ	Tests packed signed quadwords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPGTW	Tests packed signed words for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPISTRI	Compares two zero-terminated strings in XMM registers as an immediate says, returning an index in ECX; VEX form.	4
VPCMPISTRM	Compares two zero-terminated strings in XMM registers as an immediate says, returning a mask in XMM0; VEX form.	2
VPERM2F128	Builds each 128-bit half of a YMM result from either half of two sources, or zero, as an immediate selects.	2
VPERMILPD	Rearranges doubles within each 128-bit lane, controlled by an immediate or by a vector.	8
VPERMILPS	Rearranges singles within each 128-bit lane, controlled by an immediate or by a vector.	8
VPEXTRB	Copies the byte selected by an immediate from an XMM register to a general-purpose register or memory.	2
VPEXTRD	Copies the doubleword selected by an immediate from an XMM register to a general-purpose register or memory.	2
VPEXTRQ	Copies the quadword selected by an immediate from an XMM register to a general-purpose register or memory.	2
VPEXTRW	Copies the word selected by an immediate from an XMM register to a general-purpose register or memory.	3
VPHADDD	Adds adjacent pairs of doublewords within each 128-bit lane of two sources, the first source's sums going low in the lane.	2
VPHADDSW	Adds adjacent pairs of signed words within each 128-bit lane with signed saturation, the first source's sums going low.	2
VPHADDW	Adds adjacent pairs of words within each 128-bit lane of two sources, the first source's sums going low in the lane.	2
VPHMINPOSUW	Finds the smallest unsigned word of an XMM operand and returns it with its index in the low two words; VEX form.	2
VPHSUBD	Subtracts the odd doubleword from the even one in adjacent pairs within each 128-bit lane of two sources.	2
VPHSUBSW	Subtracts the odd signed word from the even one in adjacent pairs within each 128-bit lane, with signed saturation.	2
VPHSUBW	Subtracts the odd word from the even one in adjacent pairs within each 128-bit lane of two sources.	2
VPINSRB	Inserts a byte from a register or memory into an XMM register at the position an immediate gives.	2
VPINSRD	Inserts a doubleword from a register or memory into an XMM register at the position an immediate gives.	2
VPINSRQ	Inserts a quadword from a register or memory into an XMM register at the position an immediate gives.	2
VPINSRW	Inserts a word from a register or memory into an XMM register at the position an immediate gives.	2
VPMADDUBSW	Multiplies unsigned bytes of the first source by signed bytes of the second and adds adjacent products into words with signed saturation.	2
VPMADDWD	Multiplies signed words and adds adjacent products into doublewords.	2
VPMAXSB	Returns the larger of each pair of signed bytes.	2
VPMAXSD	Returns the larger of each pair of signed doublewords.	2
VPMAXSW	Returns the larger of each pair of signed words.	2
VPMAXUB	Returns the larger of each pair of unsigned bytes.	2
VPMAXUD	Returns the larger of each pair of unsigned doublewords.	2
VPMAXUW	Returns the larger of each pair of unsigned words.	2
VPMINSB	Returns the smaller of each pair of signed bytes.	2
VPMINSD	Returns the smaller of each pair of signed doublewords.	2
VPMINSW	Returns the smaller of each pair of signed words.	2
VPMINUB	Returns the smaller of each pair of unsigned bytes.	2
VPMINUD	Returns the smaller of each pair of unsigned doublewords.	2
VPMINUW	Returns the smaller of each pair of unsigned words.	2
VPMOVMSKB	Copies the top bit of each byte of an XMM or YMM register into the low bits of a general-purpose register.	1
VPMOVSXBD	Sign-extends packed bytes to doublewords.	2
VPMOVSXBQ	Sign-extends packed bytes to quadwords.	2
VPMOVSXBW	Sign-extends packed bytes to words.	2
VPMOVSXDQ	Sign-extends packed doublewords to quadwords.	2
VPMOVSXWD	Sign-extends packed words to doublewords.	2
VPMOVSXWQ	Sign-extends packed words to quadwords.	2
VPMOVZXBD	Zero-extends packed bytes to doublewords.	2
VPMOVZXBQ	Zero-extends packed bytes to quadwords.	2
VPMOVZXBW	Zero-extends packed bytes to words.	2
VPMOVZXDQ	Zero-extends packed doublewords to quadwords.	2
VPMOVZXWD	Zero-extends packed words to doublewords.	2
VPMOVZXWQ	Zero-extends packed words to quadwords.	2
VPMULDQ	Multiplies the signed low doublewords of each quadword into 64-bit products.	2
VPMULHRSW	Multiplies packed signed words as Q15 fixed-point numbers, rounding each product to a Q15 result.	2
VPMULHUW	Multiplies unsigned words and keeps the high 16 bits of each product.	2
VPMULHW	Multiplies signed words and keeps the high 16 bits of each product.	2
VPMULLD	Multiplies packed doublewords and keeps the low 32 bits of each product.	2
VPMULLW	Multiplies packed words and keeps the low 16 bits of each product.	2
VPMULUDQ	Multiplies the unsigned low doublewords of each quadword into 64-bit products.	2
VPOR	Computes the bitwise OR of two XMM or YMM sources into a separate destination (YMM with AVX2).	2
VPSADBW	Sums the absolute differences of unsigned bytes over each group of eight, giving one 16-bit sum per quadword.	2
VPSHUFB	Rearranges bytes within each 128-bit lane using an index byte per result, which zeroes the byte when its top bit is set.	2
VPSHUFD	Rearranges doublewords within each 128-bit lane as an immediate selects.	2
VPSHUFHW	Rearranges the upper four words of each 128-bit lane as an immediate selects.	2
VPSHUFLW	Rearranges the lower four words of each 128-bit lane as an immediate selects.	2
VPSIGNB	Negates, zeroes or keeps each signed byte of the first source as the matching byte of the second is negative, zero or positive.	2
VPSIGND	Negates, zeroes or keeps each doubleword of the first source as the matching one of the second is negative, zero or positive.	2
VPSIGNW	Negates, zeroes or keeps each signed word of the first source as the matching word of the second is negative, zero or positive.	2
VPSLLD	Shifts doublewords left by one count from a register or an immediate.	3
VPSLLDQ	Shifts each 128-bit lane left by a number of bytes given by an immediate.	1
VPSLLQ	Shifts quadwords left by one count from a register or an immediate.	3
VPSLLW	Shifts words left by one count from a register or an immediate.	3
VPSRAD	Shifts doublewords right arithmetically by one count from a register or an immediate.	3
VPSRAW	Shifts words right arithmetically by one count from a register or an immediate.	3
VPSRLD	Shifts doublewords right logically by one count from a register or an immediate.	3
VPSRLDQ	Shifts each 128-bit lane right by a number of bytes given by an immediate.	1
VPSRLQ	Shifts quadwords right logically by one count from a register or an immediate.	3
VPSRLW	Shifts words right logically by one count from a register or an immediate.	3
VPSUBB	Subtracts packed bytes, wrapping around on overflow.	2
VPSUBD	Subtracts packed doublewords, wrapping around on overflow.	2
VPSUBQ	Subtracts packed quadwords, wrapping around on overflow.	2
VPSUBSB	Subtracts packed signed bytes with signed saturation.	2
VPSUBSW	Subtracts packed signed words with signed saturation.	2
VPSUBUSB	Subtracts packed unsigned bytes with unsigned saturation.	2
VPSUBUSW	Subtracts packed unsigned words with unsigned saturation.	2
VPSUBW	Subtracts packed words, wrapping around on overflow.	2
VPTEST	Sets ZF if the AND of two XMM or YMM operands is all zeros and CF if the AND of the inverted first with the second is.	4
VPUNPCKHBW	Interleaves the high bytes of each 128-bit lane of two sources.	2
VPUNPCKHDQ	Interleaves the high doublewords of each 128-bit lane of two sources.	2
VPUNPCKHQDQ	Interleaves the high quadwords of each 128-bit lane of two sources.	2
VPUNPCKHWD	Interleaves the high words of each 128-bit lane of two sources.	2
VPUNPCKLBW	Interleaves the low bytes of each 128-bit lane of two sources.	2
VPUNPCKLDQ	Interleaves the low doublewords of each 128-bit lane of two sources.	2
VPUNPCKLQDQ	Interleaves the low quadwords of each 128-bit lane of two sources.	2
VPUNPCKLWD	Interleaves the low words of each 128-bit lane of two sources.	2
VPXOR	Computes the bitwise XOR of two XMM or YMM sources into a separate destination (YMM with AVX2).	2
VRCPPS	Approximates the reciprocals of packed singles in an XMM or YMM register, with a relative error of at most 1.5 times 2^-12.	4
VRCPSS	Approximates the reciprocal of the low single to within 1.5 times 2^-12; the other elements come from the first source.	2
VROUNDPD	Rounds packed doubles in an XMM or YMM register to integral values, with the rounding mode of an immediate or MXCSR.	4
VROUNDPS	Rounds packed singles in an XMM or YMM register to integral values, with the rounding mode of an immediate or MXCSR.	4
VROUNDSD	Rounds the low double of the second source to an integral value, by an immediate or MXCSR; the upper half comes from the first.	2
VROUNDSS	Rounds the low single of the second source to an integral value, by an immediate or MXCSR; the rest comes from the first.	2
VRSQRTPS	Approximates the reciprocal square roots of packed singles in an XMM or YMM register, to within 1.5 times 2^-12.	4
VRSQRTSS	Approximates the reciprocal square root of the low single to within 1.5 times 2^-12; the other elements come from the first source.	2
VSHUFPD	Picks doubles from the two sources for each position within each 128-bit lane, as an immediate selects.	4
VSHUFPS	Picks singles from the two sources for each position within each 128-bit lane, as an immediate selects.	4
VSQRTPD	Computes the square root of packed doubles.	4
VSQRTPS	Computes the square root of packed singles.	4
VSQRTSD	Computes the square root of the low double of the second source; the other elements come from the first source.	2
VSQRTSS	Computes the square root of the low single of the second source; the other elements come from the first source.	2
VSTMXCSR	Stores the MXCSR register, the SSE control and status bits, to memory; the VEX form of STMXCSR.	1
VSUBPD	Subtracts packed doubles.	4
VSUBPS	Subtracts packed singles.	4
VSUBSD	Subtracts the low doubles; the other elements come from the first source.	2
VSUBSS	Subtracts the low singles; the other elements come from the first source.	2
VTESTPD	Sets ZF and CF like VPTEST, but from the sign bits of the packed doubles alone.	4
VTESTPS	Sets ZF and CF like VPTEST, but from the sign bits of the packed singles alone.	4
VUCOMISD	Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception.	2
VUCOMISS	Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception.	2
VUNPCKHPD	Interleaves the high doubles of each 128-bit lane of two sources.	4
VUNPCKHPS	Interleaves the high singles of each 128-bit lane of two sources.	4
VUNPCKLPD	Interleaves the low doubles of each 128-bit lane of two sources.	4
VUNPCKLPS	Interleaves the low singles of each 128-bit lane of two sources.	4
VXORPD	Computes the bitwise XOR of packed doubles.	4
VXORPS	Computes the bitwise XOR of packed singles.	4
VZEROALL	Zeroes vector registers 0 to 15 (0 to 7 outside 64-bit mode) in full.	1
VZEROUPPER	Zeroes the bits above 127 of vector registers 0 to 15, which compilers do before running or calling code that may use legacy SSE.	1

CPUID and processors

XED splits AVX into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AVX. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Instructions

CPUID and processors

Sources