AVX10.1 instruction set extension

AVX10 replaces AVX-512’s long list of feature flags with one feature bit and a version number. Version 1 adds no instructions: AVX10.1 is the AVX-512 instruction set of Sapphire Rapids (the F, CD, BW, DQ, IFMA, VBMI, VBMI2, VNNI, BF16, BITALG, VPOPCNTDQ and FP16 subsets, at all three vector lengths) under the new enumeration. Granite Rapids is the first processor to report it.

Detection

CPUID.(EAX=07H,ECX=1):EDX[19] says that AVX10 is present and that CPUID leaf 24H exists.
CPUID.(EAX=24H,ECX=0):EBX[7:0] is the version. Versions are cumulative, so code written for version N checks for a version of at least N.
The operating system enables the register state exactly as for AVX-512, with XCR0 bits 1, 2, 5, 6 and 7.
The EVEX forms of VAES, VPCLMULQDQ and GFNI keep their own feature bits and need both that bit and AVX10.
AVX10 processors still set the AVX-512 feature bits, so existing software keeps working.

One vector length for all

Early revisions of the specification allowed AVX10 processors limited to 256-bit vectors, with CPUID bits for the supported lengths. Revision 4.0 (May 2025) dropped that plan: every AVX10 processor, client or server, performance or efficient core, supports 128-, 256- and 512-bit vectors, and the old length bits in leaf 24H are now reserved as 1.

In this reference

Because AVX10.1 is a set of AVX-512 subsets, every AVX-512 mnemonic of those subsets has a page here. The tables show XED’s ISA sets, such as AVX512F_512 or AVX512BW_128, and the CPUID section below gives both ways to enable each: AVX10.1, or the classic AVX-512 bits (with AVX512VL for 128- and 256-bit forms). The processor list above comes from the site’s CPU data, because XED’s chip model describes these processors by their AVX-512 ISA sets.

Instructions

Mnemonics with at least one form in AVX10.1. Each page lists all forms of the mnemonic, including those of other extensions.

Mnemonic	Summary	Forms
KADDB	Adds two 8-bit mask registers as unsigned integers.	1
KADDD	Adds two 32-bit mask registers as unsigned integers.	1
KADDQ	Adds two 64-bit mask registers as unsigned integers.	1
KADDW	Adds two 16-bit mask registers as unsigned integers.	1
KANDB	Computes the bitwise AND of two 8-bit masks.	1
KANDD	Computes the bitwise AND of two 32-bit masks.	1
KANDNB	Computes the bitwise AND of the inverted first 8-bit mask with the second.	1
KANDND	Computes the bitwise AND of the inverted first 32-bit mask with the second.	1
KANDNQ	Computes the bitwise AND of the inverted first 64-bit mask with the second.	1
KANDNW	Computes the bitwise AND of the inverted first 16-bit mask with the second.	1
KANDQ	Computes the bitwise AND of two 64-bit masks.	1
KANDW	Computes the bitwise AND of two 16-bit masks.	1
KMOVB	Moves an 8-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers.	5
KMOVD	Moves a 32-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers.	5
KMOVQ	Moves a 64-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers.	5
KMOVW	Moves a 16-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers.	5
KNOTB	Inverts every bit of an 8-bit mask.	1
KNOTD	Inverts every bit of a 32-bit mask.	1
KNOTQ	Inverts every bit of a 64-bit mask.	1
KNOTW	Inverts every bit of a 16-bit mask.	1
KORB	Computes the bitwise OR of two 8-bit masks.	1
KORD	Computes the bitwise OR of two 32-bit masks.	1
KORQ	Computes the bitwise OR of two 64-bit masks.	1
KORTESTB	ORs two 8-bit masks and sets ZF if the result is all zeros and CF if it is all ones.	1
KORTESTD	ORs two 32-bit masks and sets ZF if the result is all zeros and CF if it is all ones.	1
KORTESTQ	ORs two 64-bit masks and sets ZF if the result is all zeros and CF if it is all ones.	1
KORTESTW	ORs two 16-bit masks and sets ZF if the result is all zeros and CF if it is all ones.	1
KORW	Computes the bitwise OR of two 16-bit masks.	1
KSHIFTLB	Shifts an 8-bit mask left by an immediate count, filling with zeros.	1
KSHIFTLD	Shifts a 32-bit mask left by an immediate count, filling with zeros.	1
KSHIFTLQ	Shifts a 64-bit mask left by an immediate count, filling with zeros.	1
KSHIFTLW	Shifts a 16-bit mask left by an immediate count, filling with zeros.	1
KSHIFTRB	Shifts an 8-bit mask right by an immediate count, filling with zeros.	1
KSHIFTRD	Shifts a 32-bit mask right by an immediate count, filling with zeros.	1
KSHIFTRQ	Shifts a 64-bit mask right by an immediate count, filling with zeros.	1
KSHIFTRW	Shifts a 16-bit mask right by an immediate count, filling with zeros.	1
KTESTB	Sets ZF if the AND of two 8-bit masks is zero and CF if the AND of the inverted first with the second is zero.	1
KTESTD	Sets ZF if the AND of two 32-bit masks is zero and CF if the AND of the inverted first with the second is zero.	1
KTESTQ	Sets ZF if the AND of two 64-bit masks is zero and CF if the AND of the inverted first with the second is zero.	1
KTESTW	Sets ZF if the AND of two 16-bit masks is zero and CF if the AND of the inverted first with the second is zero.	1
KUNPCKBW	Joins the low 8 bits of two masks into a 16-bit mask, the second source forming the low half.	1
KUNPCKDQ	Joins the low 32 bits of two masks into a 64-bit mask, the second source forming the low half.	1
KUNPCKWD	Joins the low 16 bits of two masks into a 32-bit mask, the second source forming the low half.	1
KXNORB	Computes the bitwise XNOR of two 8-bit masks.	1
KXNORD	Computes the bitwise XNOR of two 32-bit masks.	1
KXNORQ	Computes the bitwise XNOR of two 64-bit masks.	1
KXNORW	Computes the bitwise XNOR of two 16-bit masks.	1
KXORB	Computes the bitwise XOR of two 8-bit masks.	1
KXORD	Computes the bitwise XOR of two 32-bit masks.	1
KXORQ	Computes the bitwise XOR of two 64-bit masks.	1
KXORW	Computes the bitwise XOR of two 16-bit masks.	1
VADDPD	Adds packed doubles.	6
VADDPH	Adds packed half-precision values.	6
VADDPS	Adds packed singles.	6
VADDSD	Adds the low doubles; the other elements come from the first source.	2
VADDSH	Adds the low half-precision values; the other elements come from the first source.	2
VADDSS	Adds the low singles; the other elements come from the first source.	2
VAESDEC	Performs one round of AES decryption on each 128-bit lane with the round key of the matching lane.	6
VAESDECLAST	Performs the last round of AES decryption on each 128-bit lane with the round key of the matching lane.	6
VAESENC	Performs one round of AES encryption on each 128-bit lane with the round key of the matching lane.	6
VAESENCLAST	Performs the last round of AES encryption on each 128-bit lane with the round key of the matching lane.	6
VALIGND	Concatenates two vectors and extracts one vector's worth of doublewords starting at an element offset given by an immediate.	6
VALIGNQ	Concatenates two vectors and extracts one vector's worth of quadwords starting at an element offset given by an immediate.	6
VANDNPD	Computes the bitwise AND of the inverted first source with the second, as packed doubles.	6
VANDNPS	Computes the bitwise AND of the inverted first source with the second, as packed singles.	6
VANDPD	Computes the bitwise AND of packed doubles.	6
VANDPS	Computes the bitwise AND of packed singles.	6
VBLENDMPD	Picks each of the packed doubles from the second source where a mask bit is set, otherwise from the first.	6
VBLENDMPS	Picks each of the packed singles from the second source where a mask bit is set, otherwise from the first.	6
VBROADCASTF32X2	Copies a group of two singles (64 bits) from memory or a register to every such group of a vector.	4
VBROADCASTF32X4	Copies a group of four singles (128 bits) from memory to every 128-bit block of a vector.	2
VBROADCASTF32X8	Copies a group of eight singles (256 bits) from memory to both halves of a ZMM register.	1
VBROADCASTF64X2	Copies a group of two doubles (128 bits) from memory to every 128-bit block of a vector.	2
VBROADCASTF64X4	Copies a group of four doubles (256 bits) from memory to both halves of a ZMM register.	1
VBROADCASTI32X2	Copies a group of two doublewords (64 bits) from memory or a register to every such group of a vector.	6
VBROADCASTI32X4	Copies a group of four doublewords (128 bits) from memory to every 128-bit block of a vector.	2
VBROADCASTI32X8	Copies a group of eight doublewords (256 bits) from memory to both halves of a ZMM register.	1
VBROADCASTI64X2	Copies a group of two quadwords (128 bits) from memory to every 128-bit block of a vector.	2
VBROADCASTI64X4	Copies a group of four quadwords (256 bits) from memory to both halves of a ZMM register.	1
VBROADCASTSD	Copies one double from memory or an XMM register to every element of a vector.	4
VBROADCASTSS	Copies one single from memory or an XMM register to every element of a vector.	6
VCMPPD	Compares packed doubles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	6
VCMPPH	Compares packed half-precision values with one of 32 predicates chosen by an immediate and writes the results to a mask register.	6
VCMPPS	Compares packed singles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	6
VCMPSD	Compares the low doubles with one of 32 predicates an immediate selects, into an all-ones or zero element (VEX) or a mask register (EVEX).	2
VCMPSH	Compares the low half-precision values with one of 32 predicates chosen by an immediate and writes the result to a mask register.	2
VCMPSS	Compares the low singles with one of 32 predicates an immediate selects, into an all-ones or zero element (VEX) or a mask register (EVEX).	2
VCOMISD	Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception.	2
VCOMISH	Compares the low half-precision values and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception.	2
VCOMISS	Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception.	2
VCOMPRESSPD	Packs the doubles selected by a mask contiguously into the low end of a register or into memory.	6
VCOMPRESSPS	Packs the singles selected by a mask contiguously into the low end of a register or into memory.	6
VCVTDQ2PD	Converts packed signed doublewords to doubles.	6
VCVTDQ2PH	Converts packed signed doublewords to half precision.	6
VCVTDQ2PS	Converts packed signed doublewords to singles.	6
VCVTNE2PS2BF16	Converts two vectors of singles into one vector of bfloat16 values, rounding to nearest even.	6
VCVTNEPS2BF16	Converts packed single-precision values to bfloat16, rounding to nearest even with denormals flushed to zero and without consulting MXCSR.	6
VCVTPD2DQ	Converts packed doubles to signed doublewords, rounding as MXCSR or the instruction selects.	6
VCVTPD2PH	Converts packed doubles to half precision, rounding as MXCSR or the instruction selects.	6
VCVTPD2PS	Converts packed doubles to singles, rounding as MXCSR or the instruction selects.	6
VCVTPD2QQ	Converts packed doubles to signed quadwords, rounding as MXCSR or the instruction selects.	6
VCVTPD2UDQ	Converts packed doubles to unsigned doublewords, rounding as MXCSR or the instruction selects.	6
VCVTPD2UQQ	Converts packed doubles to unsigned quadwords, rounding as MXCSR or the instruction selects.	6
VCVTPH2DQ	Converts packed half-precision values to signed doublewords, rounding as MXCSR or the instruction selects.	6
VCVTPH2PD	Converts packed half-precision values to doubles, which is exact.	6
VCVTPH2PS	Converts packed half-precision values to singles, which is exact.	6
VCVTPH2PSX	Converts packed half-precision values to singles like VCVTPH2PS, in the AVX512-FP16 form that also takes a broadcast memory source.	6
VCVTPH2QQ	Converts packed half-precision values to signed quadwords, rounding as MXCSR or the instruction selects.	6
VCVTPH2UDQ	Converts packed half-precision values to unsigned doublewords, rounding as MXCSR or the instruction selects.	6
VCVTPH2UQQ	Converts packed half-precision values to unsigned quadwords, rounding as MXCSR or the instruction selects.	6
VCVTPH2UW	Converts packed half-precision values to unsigned words, rounding as MXCSR or the instruction selects.	6
VCVTPH2W	Converts packed half-precision values to signed words, rounding as MXCSR or the instruction selects.	6
VCVTPS2DQ	Converts packed singles to signed doublewords, rounding as MXCSR or the instruction selects.	6
VCVTPS2PD	Converts packed singles to doubles, which is exact.	6
VCVTPS2PH	Converts packed singles to half precision, rounding as an immediate or MXCSR selects.	6
VCVTPS2PHX	Converts packed singles to half precision like VCVTPS2PH, but with a broadcast source and embedded rounding instead of an immediate.	6
VCVTPS2QQ	Converts packed singles to signed quadwords, rounding as MXCSR or the instruction selects.	6
VCVTPS2UDQ	Converts packed singles to unsigned doublewords, rounding as MXCSR or the instruction selects.	6
VCVTPS2UQQ	Converts packed singles to unsigned quadwords, rounding as MXCSR or the instruction selects.	6
VCVTQQ2PD	Converts packed signed quadwords to doubles.	6
VCVTQQ2PH	Converts packed signed quadwords to half precision.	6
VCVTQQ2PS	Converts packed signed quadwords to singles.	6
VCVTSD2SH	Converts the low double of the second source to half precision, rounding as MXCSR or the instruction selects; the rest come from the first source.	2
VCVTSD2SI	Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects.	4
VCVTSD2SS	Converts the low double of the second source to single, rounding as MXCSR or the instruction selects; the other elements come from the first source.	2
VCVTSD2USI	Converts the low double to an unsigned 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects.	4
VCVTSH2SD	Converts the low half-precision value of the second source to double, which is exact; the other elements come from the first source.	2
VCVTSH2SI	Converts the low half-precision value to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects.	4
VCVTSH2SS	Converts the low half-precision value of the second source to single, which is exact; the other elements come from the first source.	2
VCVTSH2USI	Converts the low half-precision value to an unsigned integer in a 32- or 64-bit register, rounding as MXCSR or the instruction selects.	4
VCVTSI2SD	Converts a signed 32- or 64-bit integer to double in the low element; the other elements come from the first source.	4
VCVTSI2SH	Converts a signed 32- or 64-bit integer to half precision in the low element; the other elements come from the first source.	4
VCVTSI2SS	Converts a signed 32- or 64-bit integer to single in the low element; the other elements come from the first source.	4
VCVTSS2SD	Converts the low single of the second source to double, which is exact; the other elements come from the first source.	2
VCVTSS2SH	Converts the low single of the second source to half precision, rounding as MXCSR or the instruction selects; the rest come from the first source.	2
VCVTSS2SI	Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects.	4
VCVTSS2USI	Converts the low single to an unsigned 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects.	4
VCVTTPD2DQ	Converts packed doubles to signed doublewords, truncating toward zero.	6
VCVTTPD2QQ	Converts packed doubles to signed quadwords, truncating toward zero.	6
VCVTTPD2UDQ	Converts packed doubles to unsigned doublewords, truncating toward zero.	6
VCVTTPD2UQQ	Converts packed doubles to unsigned quadwords, truncating toward zero.	6
VCVTTPH2DQ	Converts packed half-precision values to signed doublewords, truncating toward zero.	6
VCVTTPH2QQ	Converts packed half-precision values to signed quadwords, truncating toward zero.	6
VCVTTPH2UDQ	Converts packed half-precision values to unsigned doublewords, truncating toward zero.	6
VCVTTPH2UQQ	Converts packed half-precision values to unsigned quadwords, truncating toward zero.	6
VCVTTPH2UW	Converts packed half-precision values to unsigned words, truncating toward zero.	6
VCVTTPH2W	Converts packed half-precision values to signed words, truncating toward zero.	6
VCVTTPS2DQ	Converts packed singles to signed doublewords, truncating toward zero.	6
VCVTTPS2QQ	Converts packed singles to signed quadwords, truncating toward zero.	6
VCVTTPS2UDQ	Converts packed singles to unsigned doublewords, truncating toward zero.	6
VCVTTPS2UQQ	Converts packed singles to unsigned quadwords, truncating toward zero.	6
VCVTTSD2SI	Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero.	4
VCVTTSD2USI	Converts the low double to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero.	4
VCVTTSH2SI	Converts the low half-precision value to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero.	4
VCVTTSH2USI	Converts the low half-precision value to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero.	4
VCVTTSS2SI	Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero.	4
VCVTTSS2USI	Converts the low single to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero.	4
VCVTUDQ2PD	Converts packed unsigned doublewords to doubles.	6
VCVTUDQ2PH	Converts packed unsigned doublewords to half precision.	6
VCVTUDQ2PS	Converts packed unsigned doublewords to singles.	6
VCVTUQQ2PD	Converts packed unsigned quadwords to doubles.	6
VCVTUQQ2PH	Converts packed unsigned quadwords to half precision.	6
VCVTUQQ2PS	Converts packed unsigned quadwords to singles.	6
VCVTUSI2SD	Converts an unsigned 32- or 64-bit integer to double in the low element; the other elements come from the first source.	4
VCVTUSI2SH	Converts an unsigned 32- or 64-bit integer to half precision in the low element; the other elements come from the first source.	4
VCVTUSI2SS	Converts an unsigned 32- or 64-bit integer to single in the low element; the other elements come from the first source.	4
VCVTUW2PH	Converts packed unsigned words to half precision.	6
VCVTW2PH	Converts packed signed words to half precision.	6
VDBPSADBW	Sums absolute differences of 4-byte groups of the two sources into 16-bit results, after an immediate shuffles the second within each 128-bit lane.	6
VDIVPD	Divides packed doubles.	6
VDIVPH	Divides packed half-precision values.	6
VDIVPS	Divides packed singles.	6
VDIVSD	Divides the low doubles; the other elements come from the first source.	2
VDIVSH	Divides the low half-precision values; the other elements come from the first source.	2
VDIVSS	Divides the low singles; the other elements come from the first source.	2
VDPBF16PS	Multiplies pairs of bfloat16 values and adds both products to the matching single-precision accumulator.	6
VEXPANDPD	Spreads consecutive doubles from the low end of a register or from memory to the positions selected by a mask.	6
VEXPANDPS	Spreads consecutive singles from the low end of a register or from memory to the positions selected by a mask.	6
VEXTRACTF32X4	Copies the 128-bit block of singles that an immediate selects to a register or memory, masked per element.	4
VEXTRACTF32X8	Copies the 256-bit block of singles that an immediate selects to a register or memory, masked per element.	2
VEXTRACTF64X2	Copies the 128-bit block of doubles that an immediate selects to a register or memory, masked per element.	4
VEXTRACTF64X4	Copies the 256-bit block of doubles that an immediate selects to a register or memory, masked per element.	2
VEXTRACTI32X4	Copies the 128-bit block of doublewords that an immediate selects to a register or memory, masked per element.	4
VEXTRACTI32X8	Copies the 256-bit block of doublewords that an immediate selects to a register or memory, masked per element.	2
VEXTRACTI64X2	Copies the 128-bit block of quadwords that an immediate selects to a register or memory, masked per element.	4
VEXTRACTI64X4	Copies the 256-bit block of quadwords that an immediate selects to a register or memory, masked per element.	2
VEXTRACTPS	Copies the single that an immediate selects from an XMM register to a general-purpose register or memory.	2
VFCMADDCPH	Multiplies packed complex half-precision numbers by the complex conjugates of the second source and adds the products to the destination.	6
VFCMADDCSH	Multiplies the low complex half-precision number of the first source by the conjugate of the second's and adds the product to the destination.	2
VFCMULCPH	Multiplies packed complex half-precision numbers by the complex conjugates of the second source.	6
VFCMULCSH	Multiplies the low complex half-precision number of the first source by the complex conjugate of the second source's.	2
VFIXUPIMMPD	Replaces special doubles (such as NaN) of the first source with responses from a table in the second; an immediate controls exceptions.	6
VFIXUPIMMPS	Replaces special singles (such as NaN) of the first source with responses from a table in the second; an immediate controls exceptions.	6
VFIXUPIMMSD	Replaces a special low double (such as NaN) of the first source with a response from a table in the second; an immediate controls exceptions.	2
VFIXUPIMMSS	Replaces a special low single (such as NaN) of the first source with a response from a table in the second; an immediate controls exceptions.	2
VFMADD132PD	Fused multiply-add of packed doubles: first operand times third plus second, into the first.	6
VFMADD132PH	Fused multiply-add of packed half-precision values: first operand times third plus second, into the first.	6
VFMADD132PS	Fused multiply-add of packed singles: first operand times third plus second, into the first.	6
VFMADD132SD	Fused multiply-add of the low doubles: first times third plus second, into the first; the rest is unchanged.	2
VFMADD132SH	Fused multiply-add of the low half-precision values: first times third plus second, into the first; the rest is unchanged.	2
VFMADD132SS	Fused multiply-add of the low singles: first times third plus second, into the first; the rest is unchanged.	2
VFMADD213PD	Fused multiply-add of packed doubles: second operand times first plus third, into the first.	6
VFMADD213PH	Fused multiply-add of packed half-precision values: second operand times first plus third, into the first.	6
VFMADD213PS	Fused multiply-add of packed singles: second operand times first plus third, into the first.	6
VFMADD213SD	Fused multiply-add of the low doubles: second times first plus third, into the first; the rest is unchanged.	2
VFMADD213SH	Fused multiply-add of the low half-precision values: second times first plus third, into the first; the rest is unchanged.	2
VFMADD213SS	Fused multiply-add of the low singles: second times first plus third, into the first; the rest is unchanged.	2
VFMADD231PD	Fused multiply-add of packed doubles: second operand times third plus first, into the first.	6
VFMADD231PH	Fused multiply-add of packed half-precision values: second operand times third plus first, into the first.	6
VFMADD231PS	Fused multiply-add of packed singles: second operand times third plus first, into the first.	6
VFMADD231SD	Fused multiply-add of the low doubles: second times third plus first, into the first; the rest is unchanged.	2
VFMADD231SH	Fused multiply-add of the low half-precision values: second times third plus first, into the first; the rest is unchanged.	2
VFMADD231SS	Fused multiply-add of the low singles: second times third plus first, into the first; the rest is unchanged.	2
VFMADDCPH	Multiplies packed complex numbers, each a pair of half-precision values, and adds the products to the destination.	6
VFMADDCSH	Multiplies the low complex numbers, each a pair of half-precision values, and adds the product to the destination.	2
VFMADDSUB132PD	Fused multiply of packed doubles, first times third, minus the second in even elements and plus it in odd ones, into the first.	6
VFMADDSUB132PH	Fused multiply of packed half-precision values, first times third, minus the second in even elements and plus it in odd ones, into the first.	6
VFMADDSUB132PS	Fused multiply of packed singles, first times third, minus the second in even elements and plus it in odd ones, into the first.	6
VFMADDSUB213PD	Fused multiply of packed doubles, second times first, minus the third in even elements and plus it in odd ones, into the first.	6
VFMADDSUB213PH	Fused multiply of packed half-precision values, second times first, minus the third in even elements and plus it in odd ones, into the first.	6
VFMADDSUB213PS	Fused multiply of packed singles, second times first, minus the third in even elements and plus it in odd ones, into the first.	6
VFMADDSUB231PD	Fused multiply of packed doubles, second times third, minus the first in even elements and plus it in odd ones, into the first.	6
VFMADDSUB231PH	Fused multiply of packed half-precision values, second times third, minus the first in even elements and plus it in odd ones, into the first.	6
VFMADDSUB231PS	Fused multiply of packed singles, second times third, minus the first in even elements and plus it in odd ones, into the first.	6
VFMSUB132PD	Fused multiply-subtract of packed doubles: first operand times third minus second, into the first.	6
VFMSUB132PH	Fused multiply-subtract of packed half-precision values: first operand times third minus second, into the first.	6
VFMSUB132PS	Fused multiply-subtract of packed singles: first operand times third minus second, into the first.	6
VFMSUB132SD	Fused multiply-subtract of the low doubles: first times third minus second, into the first; the rest is unchanged.	2
VFMSUB132SH	Fused multiply-subtract of the low half-precision values: first times third minus second, into the first; the rest is unchanged.	2
VFMSUB132SS	Fused multiply-subtract of the low singles: first times third minus second, into the first; the rest is unchanged.	2
VFMSUB213PD	Fused multiply-subtract of packed doubles: second operand times first minus third, into the first.	6
VFMSUB213PH	Fused multiply-subtract of packed half-precision values: second operand times first minus third, into the first.	6
VFMSUB213PS	Fused multiply-subtract of packed singles: second operand times first minus third, into the first.	6
VFMSUB213SD	Fused multiply-subtract of the low doubles: second times first minus third, into the first; the rest is unchanged.	2
VFMSUB213SH	Fused multiply-subtract of the low half-precision values: second times first minus third, into the first; the rest is unchanged.	2
VFMSUB213SS	Fused multiply-subtract of the low singles: second times first minus third, into the first; the rest is unchanged.	2
VFMSUB231PD	Fused multiply-subtract of packed doubles: second operand times third minus first, into the first.	6
VFMSUB231PH	Fused multiply-subtract of packed half-precision values: second operand times third minus first, into the first.	6
VFMSUB231PS	Fused multiply-subtract of packed singles: second operand times third minus first, into the first.	6
VFMSUB231SD	Fused multiply-subtract of the low doubles: second times third minus first, into the first; the rest is unchanged.	2
VFMSUB231SH	Fused multiply-subtract of the low half-precision values: second times third minus first, into the first; the rest is unchanged.	2
VFMSUB231SS	Fused multiply-subtract of the low singles: second times third minus first, into the first; the rest is unchanged.	2
VFMSUBADD132PD	Fused multiply of packed doubles, first times third, plus the second in even elements and minus it in odd ones, into the first.	6
VFMSUBADD132PH	Fused multiply of packed half-precision values, first times third, plus the second in even elements and minus it in odd ones, into the first.	6
VFMSUBADD132PS	Fused multiply of packed singles, first times third, plus the second in even elements and minus it in odd ones, into the first.	6
VFMSUBADD213PD	Fused multiply of packed doubles, second times first, plus the third in even elements and minus it in odd ones, into the first.	6
VFMSUBADD213PH	Fused multiply of packed half-precision values, second times first, plus the third in even elements and minus it in odd ones, into the first.	6
VFMSUBADD213PS	Fused multiply of packed singles, second times first, plus the third in even elements and minus it in odd ones, into the first.	6
VFMSUBADD231PD	Fused multiply of packed doubles, second times third, plus the first in even elements and minus it in odd ones, into the first.	6
VFMSUBADD231PH	Fused multiply of packed half-precision values, second times third, plus the first in even elements and minus it in odd ones, into the first.	6
VFMSUBADD231PS	Fused multiply of packed singles, second times third, plus the first in even elements and minus it in odd ones, into the first.	6
VFMULCPH	Multiplies packed complex numbers, each a pair of half-precision values.	6
VFMULCSH	Multiplies the low complex numbers, each a pair of half-precision values.	2
VFNMADD132PD	Fused negated multiply-add of packed doubles: minus first operand times third, plus second, into the first.	6
VFNMADD132PH	Fused negated multiply-add of packed half-precision values: minus first operand times third, plus second, into the first.	6
VFNMADD132PS	Fused negated multiply-add of packed singles: minus first operand times third, plus second, into the first.	6
VFNMADD132SD	Fused negated multiply-add of the low doubles: minus first times third, plus second, into the first; the rest is unchanged.	2
VFNMADD132SH	Fused negated multiply-add of the low half-precision values: minus first times third, plus second, into the first; the rest is unchanged.	2
VFNMADD132SS	Fused negated multiply-add of the low singles: minus first times third, plus second, into the first; the rest is unchanged.	2
VFNMADD213PD	Fused negated multiply-add of packed doubles: minus second operand times first, plus third, into the first.	6
VFNMADD213PH	Fused negated multiply-add of packed half-precision values: minus second operand times first, plus third, into the first.	6
VFNMADD213PS	Fused negated multiply-add of packed singles: minus second operand times first, plus third, into the first.	6
VFNMADD213SD	Fused negated multiply-add of the low doubles: minus second times first, plus third, into the first; the rest is unchanged.	2
VFNMADD213SH	Fused negated multiply-add of the low half-precision values: minus second times first, plus third, into the first; the rest is unchanged.	2
VFNMADD213SS	Fused negated multiply-add of the low singles: minus second times first, plus third, into the first; the rest is unchanged.	2
VFNMADD231PD	Fused negated multiply-add of packed doubles: minus second operand times third, plus first, into the first.	6
VFNMADD231PH	Fused negated multiply-add of packed half-precision values: minus second operand times third, plus first, into the first.	6
VFNMADD231PS	Fused negated multiply-add of packed singles: minus second operand times third, plus first, into the first.	6
VFNMADD231SD	Fused negated multiply-add of the low doubles: minus second times third, plus first, into the first; the rest is unchanged.	2
VFNMADD231SH	Fused negated multiply-add of the low half-precision values: minus second times third, plus first, into the first; the rest is unchanged.	2
VFNMADD231SS	Fused negated multiply-add of the low singles: minus second times third, plus first, into the first; the rest is unchanged.	2
VFNMSUB132PD	Fused negated multiply-subtract of packed doubles: minus first operand times third, minus second, into the first.	6
VFNMSUB132PH	Fused negated multiply-subtract of packed half-precision values: minus first operand times third, minus second, into the first.	6
VFNMSUB132PS	Fused negated multiply-subtract of packed singles: minus first operand times third, minus second, into the first.	6
VFNMSUB132SD	Fused negated multiply-subtract of the low doubles: minus first times third, minus second, into the first; the rest is unchanged.	2
VFNMSUB132SH	Fused negated multiply-subtract of the low half-precision values: minus first times third, minus second, into the first; the rest is unchanged.	2
VFNMSUB132SS	Fused negated multiply-subtract of the low singles: minus first times third, minus second, into the first; the rest is unchanged.	2
VFNMSUB213PD	Fused negated multiply-subtract of packed doubles: minus second operand times first, minus third, into the first.	6
VFNMSUB213PH	Fused negated multiply-subtract of packed half-precision values: minus second operand times first, minus third, into the first.	6
VFNMSUB213PS	Fused negated multiply-subtract of packed singles: minus second operand times first, minus third, into the first.	6
VFNMSUB213SD	Fused negated multiply-subtract of the low doubles: minus second times first, minus third, into the first; the rest is unchanged.	2
VFNMSUB213SH	Fused negated multiply-subtract of the low half-precision values: minus second times first, minus third, into the first; the rest is unchanged.	2
VFNMSUB213SS	Fused negated multiply-subtract of the low singles: minus second times first, minus third, into the first; the rest is unchanged.	2
VFNMSUB231PD	Fused negated multiply-subtract of packed doubles: minus second operand times third, minus first, into the first.	6
VFNMSUB231PH	Fused negated multiply-subtract of packed half-precision values: minus second operand times third, minus first, into the first.	6
VFNMSUB231PS	Fused negated multiply-subtract of packed singles: minus second operand times third, minus first, into the first.	6
VFNMSUB231SD	Fused negated multiply-subtract of the low doubles: minus second times third, minus first, into the first; the rest is unchanged.	2
VFNMSUB231SH	Fused negated multiply-subtract of the low half-precision values: minus second times third, minus first, into the first; the rest is unchanged.	2
VFNMSUB231SS	Fused negated multiply-subtract of the low singles: minus second times third, minus first, into the first; the rest is unchanged.	2
VFPCLASSPD	Tests packed doubles for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register.	6
VFPCLASSPH	Tests packed half-precision values for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register.	6
VFPCLASSPS	Tests packed singles for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register.	6
VFPCLASSSD	Tests the low double for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register.	2
VFPCLASSSH	Tests the low half-precision value for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register.	2
VFPCLASSSS	Tests the low single for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register.	2
VGATHERDPD	Loads doubles from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	3
VGATHERDPS	Loads singles from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	3
VGATHERQPD	Loads doubles from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	3
VGATHERQPS	Loads singles from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	3
VGETEXPPD	Extracts the unbiased exponent of packed doubles as floating-point numbers.	6
VGETEXPPH	Extracts the unbiased exponent of packed half-precision values as floating-point numbers.	6
VGETEXPPS	Extracts the unbiased exponent of packed singles as floating-point numbers.	6
VGETEXPSD	Extracts the unbiased exponent of the low double of the second source as a floating-point number; the other elements come from the first source.	2
VGETEXPSH	Extracts the unbiased exponent of the low half-precision value of the second source as a float; the other elements come from the first source.	2
VGETEXPSS	Extracts the unbiased exponent of the low single of the second source as a floating-point number; the other elements come from the first source.	2
VGETMANTPD	Extracts the normalized mantissa of packed doubles, with the interval and sign handling chosen by an immediate.	6
VGETMANTPH	Extracts the normalized mantissa of packed half-precision values, with the interval and sign handling chosen by an immediate.	6
VGETMANTPS	Extracts the normalized mantissa of packed singles, with the interval and sign handling chosen by an immediate.	6
VGETMANTSD	Extracts the normalized mantissa of the low double of the second source, as an immediate selects; the other elements come from the first source.	2
VGETMANTSH	Extracts the normalized mantissa of the low half-precision value of the second source, as an immediate selects; the rest come from the first source.	2
VGETMANTSS	Extracts the normalized mantissa of the low single of the second source, as an immediate selects; the other elements come from the first source.	2
VGF2P8AFFINEINVQB	Replaces each byte with its inverse in GF(2^8), then applies an affine transformation given by an 8x8 bit matrix and an immediate constant.	6
VGF2P8AFFINEQB	Applies an affine transformation to each byte, given by an 8x8 bit matrix from the second source and an immediate constant.	6
VGF2P8MULB	Multiplies bytes in the finite field GF(2^8) defined by the AES polynomial x^8 + x^4 + x^3 + x + 1.	6
VINSERTF32X4	Replaces the 128-bit block that an immediate selects with four singles from a register or memory.	4
VINSERTF32X8	Replaces the 256-bit block that an immediate selects with eight singles from a register or memory.	2
VINSERTF64X2	Replaces the 128-bit block that an immediate selects with two doubles from a register or memory.	4
VINSERTF64X4	Replaces the 256-bit block that an immediate selects with four doubles from a register or memory.	2
VINSERTI32X4	Replaces the 128-bit block that an immediate selects with four doublewords from a register or memory.	4
VINSERTI32X8	Replaces the 256-bit block that an immediate selects with eight doublewords from a register or memory.	2
VINSERTI64X2	Replaces the 128-bit block that an immediate selects with two quadwords from a register or memory.	4
VINSERTI64X4	Replaces the 256-bit block that an immediate selects with four quadwords from a register or memory.	2
VINSERTPS	Inserts a single from a register or memory into an XMM register at the position an immediate gives, and can zero other elements.	2
VMAXPD	Returns the larger of each pair of packed doubles, or the second operand if either is NaN or both are zero.	6
VMAXPH	Returns the larger of each pair of packed half-precision values, or the second operand if either is NaN or both are zero.	6
VMAXPS	Returns the larger of each pair of packed singles, or the second operand if either is NaN or both are zero.	6
VMAXSD	Returns the larger of the low doubles, or the second operand if either is NaN or both are zero; the other elements come from the first source.	2
VMAXSH	Returns the larger low half-precision value, or the second operand if either is NaN or both are zero; the other elements come from the first source.	2
VMAXSS	Returns the larger of the low singles, or the second operand if either is NaN or both are zero; the other elements come from the first source.	2
VMINPD	Returns the smaller of each pair of packed doubles, or the second operand if either is NaN or both are zero.	6
VMINPH	Returns the smaller of each pair of packed half-precision values, or the second operand if either is NaN or both are zero.	6
VMINPS	Returns the smaller of each pair of packed singles, or the second operand if either is NaN or both are zero.	6
VMINSD	Returns the smaller of the low doubles, or the second operand if either is NaN or both are zero; the other elements come from the first source.	2
VMINSH	Returns the smaller low half-precision value, or the second operand if either is NaN or both are zero; the other elements come from the first source.	2
VMINSS	Returns the smaller of the low singles, or the second operand if either is NaN or both are zero; the other elements come from the first source.	2
VMOVAPD	Moves packed doubles between registers and memory that must be aligned to the vector size.	9
VMOVAPS	Moves packed singles between registers and memory that must be aligned to the vector size.	9
VMOVD	Moves 32 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form.	4
VMOVDDUP	Duplicates each even-numbered double into the next odd position.	6
VMOVDQA32	Moves integer vectors between registers and aligned memory, masked at doubleword granularity.	9
VMOVDQA64	Moves integer vectors between registers and aligned memory, masked at quadword granularity.	9
VMOVDQU16	Moves integer vectors between registers and memory without an alignment requirement, masked at word granularity.	9
VMOVDQU32	Moves integer vectors between registers and memory without an alignment requirement, masked at doubleword granularity.	9
VMOVDQU64	Moves integer vectors between registers and memory without an alignment requirement, masked at quadword granularity.	9
VMOVDQU8	Moves integer vectors between registers and memory without an alignment requirement, masked at byte granularity.	9
VMOVHLPS	Moves the high two singles of the second source into the low half of the result, the high half coming from the first source.	1
VMOVHPD	Loads a double from memory into the high half of an XMM register, or stores the high double to memory.	2
VMOVHPS	Loads two singles from memory into the high half of an XMM register, or stores the high two to memory.	2
VMOVLHPS	Moves the low two singles of the second source into the high half of the result, the low half coming from the first source.	1
VMOVLPD	Loads a double from memory into the low half of an XMM register, or stores the low double to memory.	2
VMOVLPS	Loads two singles from memory into the low half of an XMM register, or stores the low two to memory.	2
VMOVNTDQ	Stores an integer vector to aligned memory with a non-temporal hint that avoids polluting the caches.	3
VMOVNTDQA	Loads a vector from aligned memory with a non-temporal hint, which lets it read write-combining memory efficiently.	3
VMOVNTPD	Stores packed doubles to aligned memory with a non-temporal hint that avoids polluting the caches.	3
VMOVNTPS	Stores packed singles to aligned memory with a non-temporal hint that avoids polluting the caches.	3
VMOVQ	Moves a quadword between an XMM register and a general-purpose register, memory or another XMM register, zeroing the rest of a vector destination.	5
VMOVSD	Moves the low double between XMM registers or to and from memory; a load zeroes the rest of the register.	3
VMOVSH	Moves the low half-precision value between XMM registers or to and from memory; a load zeroes the rest of the register.	3
VMOVSHDUP	Duplicates each odd-numbered single into the even position below it.	6
VMOVSLDUP	Duplicates each even-numbered single into the odd position above it.	6
VMOVSS	Moves the low single between XMM registers or to and from memory; a load zeroes the rest of the register.	3
VMOVUPD	Moves packed doubles between registers and memory without an alignment requirement.	9
VMOVUPS	Moves packed singles between registers and memory without an alignment requirement.	9
VMOVW	Moves 16 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form.	4
VMULPD	Multiplies packed doubles.	6
VMULPH	Multiplies packed half-precision values.	6
VMULPS	Multiplies packed singles.	6
VMULSD	Multiplies the low doubles; the other elements come from the first source.	2
VMULSH	Multiplies the low half-precision values; the other elements come from the first source.	2
VMULSS	Multiplies the low singles; the other elements come from the first source.	2
VORPD	Computes the bitwise OR of packed doubles.	6
VORPS	Computes the bitwise OR of packed singles.	6
VPABSB	Computes the absolute value of packed signed bytes.	6
VPABSD	Computes the absolute value of packed signed doublewords.	6
VPABSQ	Computes the absolute value of packed signed quadwords.	6
VPABSW	Computes the absolute value of packed signed words.	6
VPACKSSDW	Narrows signed doublewords from two sources to words with signed saturation.	6
VPACKSSWB	Narrows signed words from two sources to bytes with signed saturation.	6
VPACKUSDW	Narrows signed doublewords from two sources to words with unsigned saturation.	6
VPACKUSWB	Narrows signed words from two sources to bytes with unsigned saturation.	6
VPADDB	Adds packed bytes, wrapping around on overflow.	6
VPADDD	Adds packed doublewords, wrapping around on overflow.	6
VPADDQ	Adds packed quadwords, wrapping around on overflow.	6
VPADDSB	Adds packed signed bytes with signed saturation.	6
VPADDSW	Adds packed signed words with signed saturation.	6
VPADDUSB	Adds packed unsigned bytes with unsigned saturation.	6
VPADDUSW	Adds packed unsigned words with unsigned saturation.	6
VPADDW	Adds packed words, wrapping around on overflow.	6
VPALIGNR	Concatenates two sources in each 128-bit lane and extracts 16 bytes starting at a byte offset given by an immediate.	6
VPANDD	Computes the bitwise AND of two vectors, masked at doubleword granularity.	6
VPANDND	Computes the bitwise AND of the inverted first source with the second, masked at doubleword granularity.	6
VPANDNQ	Computes the bitwise AND of the inverted first source with the second, masked at quadword granularity.	6
VPANDQ	Computes the bitwise AND of two vectors, masked at quadword granularity.	6
VPAVGB	Computes the rounded average of packed unsigned bytes.	6
VPAVGW	Computes the rounded average of packed unsigned words.	6
VPBLENDMB	Picks each byte from the second source where a mask bit is set, otherwise from the first.	6
VPBLENDMD	Picks each doubleword from the second source where a mask bit is set, otherwise from the first.	6
VPBLENDMQ	Picks each quadword from the second source where a mask bit is set, otherwise from the first.	6
VPBLENDMW	Picks each word from the second source where a mask bit is set, otherwise from the first.	6
VPBROADCASTB	Copies one byte from a register or memory to every byte of a vector.	9
VPBROADCASTD	Copies one doubleword from a register or memory to every doubleword of a vector.	9
VPBROADCASTMB2Q	Copies the low 8 bits of a mask register, zero-extended, to every quadword.	3
VPBROADCASTMW2D	Copies the low 16 bits of a mask register, zero-extended, to every doubleword.	3
VPBROADCASTQ	Copies one quadword from a register or memory to every quadword of a vector.	9
VPBROADCASTW	Copies one word from a register or memory to every word of a vector.	9
VPCLMULQDQ	Carry-less multiplies one quadword of each source, chosen by an immediate, into a 128-bit product in each 128-bit lane.	6
VPCMPB	Compares packed signed bytes with a predicate chosen by an immediate and writes the results to a mask register.	6
VPCMPD	Compares packed signed doublewords with a predicate chosen by an immediate and writes the results to a mask register.	6
VPCMPEQB	Compares packed bytes for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	6
VPCMPEQD	Compares packed doublewords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	6
VPCMPEQQ	Compares packed quadwords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	6
VPCMPEQW	Compares packed words for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	6
VPCMPGTB	Tests packed signed bytes for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	6
VPCMPGTD	Tests packed signed doublewords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	6
VPCMPGTQ	Tests packed signed quadwords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	6
VPCMPGTW	Tests packed signed words for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	6
VPCMPQ	Compares packed signed quadwords with a predicate chosen by an immediate and writes the results to a mask register.	6
VPCMPUB	Compares packed unsigned bytes with a predicate chosen by an immediate and writes the results to a mask register.	6
VPCMPUD	Compares packed unsigned doublewords with a predicate chosen by an immediate and writes the results to a mask register.	6
VPCMPUQ	Compares packed unsigned quadwords with a predicate chosen by an immediate and writes the results to a mask register.	6
VPCMPUW	Compares packed unsigned words with a predicate chosen by an immediate and writes the results to a mask register.	6
VPCMPW	Compares packed signed words with a predicate chosen by an immediate and writes the results to a mask register.	6
VPCOMPRESSB	Packs the bytes selected by a mask contiguously into the low end of a register or into memory.	6
VPCOMPRESSD	Packs the doublewords selected by a mask contiguously into the low end of a register or into memory.	6
VPCOMPRESSQ	Packs the quadwords selected by a mask contiguously into the low end of a register or into memory.	6
VPCOMPRESSW	Packs the words selected by a mask contiguously into the low end of a register or into memory.	6
VPCONFLICTD	For each doubleword, sets a bit for every lower-numbered element of the source that holds the same value.	6
VPCONFLICTQ	For each quadword, sets a bit for every lower-numbered element of the source that holds the same value.	6
VPDPBUSD	Multiplies unsigned bytes of the first source by signed bytes of the second and adds each group of four products to a 32-bit accumulator.	6
VPDPBUSDS	Multiplies unsigned bytes of the first source by signed bytes of the second and adds each group of four products to a 32-bit accumulator, saturating.	6
VPDPWSSD	Multiplies pairs of signed words, adds both products to the matching 32-bit accumulator.	6
VPDPWSSDS	Multiplies pairs of signed words and adds both products to the matching 32-bit accumulator with signed saturation.	6
VPERMB	Rearranges the bytes of a vector across the whole register using an index vector.	6
VPERMD	Rearranges the doublewords of a vector across the whole register using an index vector.	4
VPERMI2B	Selects bytes from two tables with an index vector that the result then overwrites.	6
VPERMI2D	Selects doublewords from two tables with an index vector that the result then overwrites.	6
VPERMI2PD	Selects doubles from two tables with an index vector that the result then overwrites.	6
VPERMI2PS	Selects singles from two tables with an index vector that the result then overwrites.	6
VPERMI2Q	Selects quadwords from two tables with an index vector that the result then overwrites.	6
VPERMI2W	Selects words from two tables with an index vector that the result then overwrites.	6
VPERMILPD	Rearranges doubles within each 128-bit lane, controlled by an immediate or by a vector.	12
VPERMILPS	Rearranges singles within each 128-bit lane, controlled by an immediate or by a vector.	12
VPERMPD	Rearranges doubles across the whole register, controlled by an immediate or by an index vector.	8
VPERMPS	Rearranges singles across the whole register using an index vector.	4
VPERMQ	Rearranges quadwords across the whole register, controlled by an immediate or by an index vector.	8
VPERMT2B	Selects bytes from two tables with an index vector, the result overwriting the first table.	6
VPERMT2D	Selects doublewords from two tables with an index vector, the result overwriting the first table.	6
VPERMT2PD	Selects doubles from two tables with an index vector, the result overwriting the first table.	6
VPERMT2PS	Selects singles from two tables with an index vector, the result overwriting the first table.	6
VPERMT2Q	Selects quadwords from two tables with an index vector, the result overwriting the first table.	6
VPERMT2W	Selects words from two tables with an index vector, the result overwriting the first table.	6
VPERMW	Rearranges the words of a vector across the whole register using an index vector.	6
VPEXPANDB	Spreads consecutive bytes from the low end of a register or from memory to the positions selected by a mask.	6
VPEXPANDD	Spreads consecutive doublewords from the low end of a register or from memory to the positions selected by a mask.	6
VPEXPANDQ	Spreads consecutive quadwords from the low end of a register or from memory to the positions selected by a mask.	6
VPEXPANDW	Spreads consecutive words from the low end of a register or from memory to the positions selected by a mask.	6
VPEXTRB	Copies the byte selected by an immediate from an XMM register to a general-purpose register or memory.	2
VPEXTRD	Copies the doubleword selected by an immediate from an XMM register to a general-purpose register or memory.	2
VPEXTRQ	Copies the quadword selected by an immediate from an XMM register to a general-purpose register or memory.	2
VPEXTRW	Copies the word selected by an immediate from an XMM register to a general-purpose register or memory.	3
VPGATHERDD	Loads doublewords from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	3
VPGATHERDQ	Loads quadwords from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	3
VPGATHERQD	Loads doublewords from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	3
VPGATHERQQ	Loads quadwords from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	3
VPINSRB	Inserts a byte from a register or memory into an XMM register at the position an immediate gives.	2
VPINSRD	Inserts a doubleword from a register or memory into an XMM register at the position an immediate gives.	2
VPINSRQ	Inserts a quadword from a register or memory into an XMM register at the position an immediate gives.	2
VPINSRW	Inserts a word from a register or memory into an XMM register at the position an immediate gives.	2
VPLZCNTD	Counts the leading zero bits of each doubleword.	6
VPLZCNTQ	Counts the leading zero bits of each quadword.	6
VPMADD52HUQ	Multiplies the low 52 bits of packed unsigned quadwords into 104-bit products and adds the high 52 bits of each product to a 64-bit accumulator.	6
VPMADD52LUQ	Multiplies the low 52 bits of packed unsigned quadwords into 104-bit products and adds the low 52 bits of each product to a 64-bit accumulator.	6
VPMADDUBSW	Multiplies unsigned bytes of the first source by signed bytes of the second and adds adjacent products into words with signed saturation.	6
VPMADDWD	Multiplies signed words and adds adjacent products into doublewords.	6
VPMAXSB	Returns the larger of each pair of signed bytes.	6
VPMAXSD	Returns the larger of each pair of signed doublewords.	6
VPMAXSQ	Returns the larger of each pair of signed quadwords.	6
VPMAXSW	Returns the larger of each pair of signed words.	6
VPMAXUB	Returns the larger of each pair of unsigned bytes.	6
VPMAXUD	Returns the larger of each pair of unsigned doublewords.	6
VPMAXUQ	Returns the larger of each pair of unsigned quadwords.	6
VPMAXUW	Returns the larger of each pair of unsigned words.	6
VPMINSB	Returns the smaller of each pair of signed bytes.	6
VPMINSD	Returns the smaller of each pair of signed doublewords.	6
VPMINSQ	Returns the smaller of each pair of signed quadwords.	6
VPMINSW	Returns the smaller of each pair of signed words.	6
VPMINUB	Returns the smaller of each pair of unsigned bytes.	6
VPMINUD	Returns the smaller of each pair of unsigned doublewords.	6
VPMINUQ	Returns the smaller of each pair of unsigned quadwords.	6
VPMINUW	Returns the smaller of each pair of unsigned words.	6
VPMOVB2M	Sets each bit of a mask register from the sign bit of the corresponding byte.	3
VPMOVD2M	Sets each bit of a mask register from the sign bit of the corresponding doubleword.	3
VPMOVDB	Narrows packed doublewords to bytes by truncation.	6
VPMOVDW	Narrows packed doublewords to words by truncation.	6
VPMOVM2B	Sets each byte to all ones or all zeros according to the corresponding mask bit.	3
VPMOVM2D	Sets each doubleword to all ones or all zeros according to the corresponding mask bit.	3
VPMOVM2Q	Sets each quadword to all ones or all zeros according to the corresponding mask bit.	3
VPMOVM2W	Sets each word to all ones or all zeros according to the corresponding mask bit.	3
VPMOVQ2M	Sets each bit of a mask register from the sign bit of the corresponding quadword.	3
VPMOVQB	Narrows packed quadwords to bytes by truncation.	6
VPMOVQD	Narrows packed quadwords to doublewords by truncation.	6
VPMOVQW	Narrows packed quadwords to words by truncation.	6
VPMOVSDB	Narrows packed signed doublewords to bytes with signed saturation.	6
VPMOVSDW	Narrows packed signed doublewords to words with signed saturation.	6
VPMOVSQB	Narrows packed signed quadwords to bytes with signed saturation.	6
VPMOVSQD	Narrows packed signed quadwords to doublewords with signed saturation.	6
VPMOVSQW	Narrows packed signed quadwords to words with signed saturation.	6
VPMOVSWB	Narrows packed signed words to bytes with signed saturation.	6
VPMOVSXBD	Sign-extends packed bytes to doublewords.	6
VPMOVSXBQ	Sign-extends packed bytes to quadwords.	6
VPMOVSXBW	Sign-extends packed bytes to words.	6
VPMOVSXDQ	Sign-extends packed doublewords to quadwords.	6
VPMOVSXWD	Sign-extends packed words to doublewords.	6
VPMOVSXWQ	Sign-extends packed words to quadwords.	6
VPMOVUSDB	Narrows packed unsigned doublewords to bytes with unsigned saturation.	6
VPMOVUSDW	Narrows packed unsigned doublewords to words with unsigned saturation.	6
VPMOVUSQB	Narrows packed unsigned quadwords to bytes with unsigned saturation.	6
VPMOVUSQD	Narrows packed unsigned quadwords to doublewords with unsigned saturation.	6
VPMOVUSQW	Narrows packed unsigned quadwords to words with unsigned saturation.	6
VPMOVUSWB	Narrows packed unsigned words to bytes with unsigned saturation.	6
VPMOVW2M	Sets each bit of a mask register from the sign bit of the corresponding word.	3
VPMOVWB	Narrows packed words to bytes by truncation.	6
VPMOVZXBD	Zero-extends packed bytes to doublewords.	6
VPMOVZXBQ	Zero-extends packed bytes to quadwords.	6
VPMOVZXBW	Zero-extends packed bytes to words.	6
VPMOVZXDQ	Zero-extends packed doublewords to quadwords.	6
VPMOVZXWD	Zero-extends packed words to doublewords.	6
VPMOVZXWQ	Zero-extends packed words to quadwords.	6
VPMULDQ	Multiplies the signed low doublewords of each quadword into 64-bit products.	6
VPMULHRSW	Multiplies packed signed words as Q15 fixed-point numbers, rounding each product to a Q15 result.	6
VPMULHUW	Multiplies unsigned words and keeps the high 16 bits of each product.	6
VPMULHW	Multiplies signed words and keeps the high 16 bits of each product.	6
VPMULLD	Multiplies packed doublewords and keeps the low 32 bits of each product.	6
VPMULLQ	Multiplies packed quadwords and keeps the low 64 bits of each product.	6
VPMULLW	Multiplies packed words and keeps the low 16 bits of each product.	6
VPMULTISHIFTQB	For each byte of the result, takes 8 bits from the matching quadword of the second source at a bit offset given by a control byte of the first.	6
VPMULUDQ	Multiplies the unsigned low doublewords of each quadword into 64-bit products.	6
VPOPCNTB	Counts the set bits in each byte.	6
VPOPCNTD	Counts the set bits in each doubleword.	6
VPOPCNTQ	Counts the set bits in each quadword.	6
VPOPCNTW	Counts the set bits in each word.	6
VPORD	Computes the bitwise OR of two vectors, masked at doubleword granularity.	6
VPORQ	Computes the bitwise OR of two vectors, masked at quadword granularity.	6
VPROLD	Rotates each doubleword left by an immediate count.	6
VPROLQ	Rotates each quadword left by an immediate count.	6
VPROLVD	Rotates each doubleword left by the count in the matching element of the second source.	6
VPROLVQ	Rotates each quadword left by the count in the matching element of the second source.	6
VPRORD	Rotates each doubleword right by an immediate count.	6
VPRORQ	Rotates each quadword right by an immediate count.	6
VPRORVD	Rotates each doubleword right by the count in the matching element of the second source.	6
VPRORVQ	Rotates each quadword right by the count in the matching element of the second source.	6
VPSADBW	Sums the absolute differences of unsigned bytes over each group of eight, giving one 16-bit sum per quadword.	6
VPSCATTERDD	Stores doublewords to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	3
VPSCATTERDQ	Stores quadwords to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	3
VPSCATTERQD	Stores doublewords to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	3
VPSCATTERQQ	Stores quadwords to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	3
VPSHLDD	Joins each doubleword of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half.	6
VPSHLDQ	Joins each quadword of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half.	6
VPSHLDVD	Joins each doubleword of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half.	6
VPSHLDVQ	Joins each quadword of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half.	6
VPSHLDVW	Joins each word of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half.	6
VPSHLDW	Joins each word of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half.	6
VPSHRDD	Joins each doubleword of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half.	6
VPSHRDQ	Joins each quadword of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half.	6
VPSHRDVD	Joins each doubleword of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half.	6
VPSHRDVQ	Joins each quadword of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half.	6
VPSHRDVW	Joins each word of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half.	6
VPSHRDW	Joins each word of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half.	6
VPSHUFB	Rearranges bytes within each 128-bit lane using an index byte per result, which zeroes the byte when its top bit is set.	6
VPSHUFBITQMB	Selects, for each byte of the second source, one bit of the matching quadword of the first and writes the bits to a mask register.	6
VPSHUFD	Rearranges doublewords within each 128-bit lane as an immediate selects.	6
VPSHUFHW	Rearranges the upper four words of each 128-bit lane as an immediate selects.	6
VPSHUFLW	Rearranges the lower four words of each 128-bit lane as an immediate selects.	6
VPSLLD	Shifts doublewords left by one count from a register or an immediate.	12
VPSLLDQ	Shifts each 128-bit lane left by a number of bytes given by an immediate.	6
VPSLLQ	Shifts quadwords left by one count from a register or an immediate.	12
VPSLLVD	Shifts each doubleword left by the count in the matching element of the second source.	6
VPSLLVQ	Shifts each quadword left by the count in the matching element of the second source.	6
VPSLLVW	Shifts each word left by the count in the matching element of the second source.	6
VPSLLW	Shifts words left by one count from a register or an immediate.	12
VPSRAD	Shifts doublewords right arithmetically by one count from a register or an immediate.	12
VPSRAQ	Shifts quadwords right arithmetically by one count from a register or an immediate.	12
VPSRAVD	Shifts each doubleword right arithmetically by the count in the matching element of the second source.	6
VPSRAVQ	Shifts each quadword right arithmetically by the count in the matching element of the second source.	6
VPSRAVW	Shifts each word right arithmetically by the count in the matching element of the second source.	6
VPSRAW	Shifts words right arithmetically by one count from a register or an immediate.	12
VPSRLD	Shifts doublewords right logically by one count from a register or an immediate.	12
VPSRLDQ	Shifts each 128-bit lane right by a number of bytes given by an immediate.	6
VPSRLQ	Shifts quadwords right logically by one count from a register or an immediate.	12
VPSRLVD	Shifts each doubleword right logically by the count in the matching element of the second source.	6
VPSRLVQ	Shifts each quadword right logically by the count in the matching element of the second source.	6
VPSRLVW	Shifts each word right logically by the count in the matching element of the second source.	6
VPSRLW	Shifts words right logically by one count from a register or an immediate.	12
VPSUBB	Subtracts packed bytes, wrapping around on overflow.	6
VPSUBD	Subtracts packed doublewords, wrapping around on overflow.	6
VPSUBQ	Subtracts packed quadwords, wrapping around on overflow.	6
VPSUBSB	Subtracts packed signed bytes with signed saturation.	6
VPSUBSW	Subtracts packed signed words with signed saturation.	6
VPSUBUSB	Subtracts packed unsigned bytes with unsigned saturation.	6
VPSUBUSW	Subtracts packed unsigned words with unsigned saturation.	6
VPSUBW	Subtracts packed words, wrapping around on overflow.	6
VPTERNLOGD	Computes any bitwise function of three inputs, given as an 8-bit truth table in an immediate, masked at doubleword granularity.	6
VPTERNLOGQ	Computes any bitwise function of three inputs, given as an 8-bit truth table in an immediate, masked at quadword granularity.	6
VPTESTMB	Sets a mask bit for each pair of bytes whose AND is not zero.	6
VPTESTMD	Sets a mask bit for each pair of doublewords whose AND is not zero.	6
VPTESTMQ	Sets a mask bit for each pair of quadwords whose AND is not zero.	6
VPTESTMW	Sets a mask bit for each pair of words whose AND is not zero.	6
VPTESTNMB	Sets a mask bit for each pair of bytes whose AND is zero.	6
VPTESTNMD	Sets a mask bit for each pair of doublewords whose AND is zero.	6
VPTESTNMQ	Sets a mask bit for each pair of quadwords whose AND is zero.	6
VPTESTNMW	Sets a mask bit for each pair of words whose AND is zero.	6
VPUNPCKHBW	Interleaves the high bytes of each 128-bit lane of two sources.	6
VPUNPCKHDQ	Interleaves the high doublewords of each 128-bit lane of two sources.	6
VPUNPCKHQDQ	Interleaves the high quadwords of each 128-bit lane of two sources.	6
VPUNPCKHWD	Interleaves the high words of each 128-bit lane of two sources.	6
VPUNPCKLBW	Interleaves the low bytes of each 128-bit lane of two sources.	6
VPUNPCKLDQ	Interleaves the low doublewords of each 128-bit lane of two sources.	6
VPUNPCKLQDQ	Interleaves the low quadwords of each 128-bit lane of two sources.	6
VPUNPCKLWD	Interleaves the low words of each 128-bit lane of two sources.	6
VPXORD	Computes the bitwise XOR of two vectors, masked at doubleword granularity.	6
VPXORQ	Computes the bitwise XOR of two vectors, masked at quadword granularity.	6
VRANGEPD	Computes the minimum, maximum, or value of smaller or larger magnitude of packed doubles, as an immediate selects along with the sign of the result.	6
VRANGEPS	Computes the minimum, maximum, or value of smaller or larger magnitude of packed singles, as an immediate selects along with the sign of the result.	6
VRANGESD	Computes the minimum, maximum, or smaller or larger magnitude of the low doubles, as an immediate selects; the rest come from the first source.	2
VRANGESS	Computes the minimum, maximum, or smaller or larger magnitude of the low singles, as an immediate selects; the rest come from the first source.	2
VRCP14PD	Approximates the reciprocal of packed doubles with a relative error below 2^-14.	6
VRCP14PS	Approximates the reciprocal of packed singles with a relative error below 2^-14.	6
VRCP14SD	Approximates the reciprocal of the low double of the second source with a relative error below 2^-14; the other elements come from the first source.	2
VRCP14SS	Approximates the reciprocal of the low single of the second source with a relative error below 2^-14; the other elements come from the first source.	2
VRCPPH	Approximates the reciprocal of packed half-precision values with a relative error below 2^-11 + 2^-14.	6
VRCPSH	Approximates the reciprocal of the second source's low half-precision value, relative error below 2^-11 + 2^-14; the rest come from the first source.	2
VREDUCEPD	Subtracts from packed doubles their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument.	6
VREDUCEPH	Subtracts from packed half-precision values their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument.	6
VREDUCEPS	Subtracts from packed singles their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument.	6
VREDUCESD	Subtracts from the low double of the second source its value rounded to the fraction bits an immediate gives; the rest come from the first source.	2
VREDUCESH	Subtracts from the second source's low half-precision value that value rounded to an immediate's precision; the rest come from the first source.	2
VREDUCESS	Subtracts from the low single of the second source its value rounded to the fraction bits an immediate gives; the rest come from the first source.	2
VRNDSCALEPD	Rounds packed doubles to the number of fraction bits and with the rounding mode that an immediate gives.	6
VRNDSCALEPH	Rounds packed half-precision values to the number of fraction bits and with the rounding mode that an immediate gives.	6
VRNDSCALEPS	Rounds packed singles to the number of fraction bits and with the rounding mode that an immediate gives.	6
VRNDSCALESD	Rounds the low double of the second source to the fraction bits and rounding mode an immediate gives; the rest come from the first source.	2
VRNDSCALESH	Rounds the second source's low half-precision value to the fraction bits and rounding mode an immediate gives; the rest come from the first source.	2
VRNDSCALESS	Rounds the low single of the second source to the fraction bits and rounding mode an immediate gives; the rest come from the first source.	2
VRSQRT14PD	Approximates the reciprocal square root of packed doubles with a relative error below 2^-14.	6
VRSQRT14PS	Approximates the reciprocal square root of packed singles with a relative error below 2^-14.	6
VRSQRT14SD	Approximates the reciprocal square root of the second source's low double, relative error below 2^-14; the rest come from the first source.	2
VRSQRT14SS	Approximates the reciprocal square root of the second source's low single, relative error below 2^-14; the rest come from the first source.	2
VRSQRTPH	Approximates the reciprocal square root of packed half-precision values with a relative error below 2^-11 + 2^-14.	6
VRSQRTSH	Approximates 1/sqrt(x) for the second source's low half-precision value, relative error below 2^-11 + 2^-14; the rest come from the first source.	2
VSCALEFPD	Multiplies packed doubles by 2 raised to the floor of the matching values of the second source.	6
VSCALEFPH	Multiplies packed half-precision values by 2 raised to the floor of the matching values of the second source.	6
VSCALEFPS	Multiplies packed singles by 2 raised to the floor of the matching values of the second source.	6
VSCALEFSD	Multiplies the low double by 2 raised to the floor of the low value of the second source; the other elements come from the first source.	2
VSCALEFSH	Multiplies the low half-precision value by 2 to the floor of the second source's low value; the other elements come from the first source.	2
VSCALEFSS	Multiplies the low single by 2 raised to the floor of the low value of the second source; the other elements come from the first source.	2
VSCATTERDPD	Stores doubles to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	3
VSCATTERDPS	Stores singles to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	3
VSCATTERQPD	Stores doubles to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	3
VSCATTERQPS	Stores singles to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	3
VSHUFF32X4	Picks 128-bit blocks of singles from the two sources as an immediate selects, the lower half of the result from the first source.	4
VSHUFF64X2	Picks 128-bit blocks of doubles from the two sources as an immediate selects, the lower half of the result from the first source.	4
VSHUFI32X4	Picks 128-bit blocks of doublewords from the two sources as an immediate selects, the lower half of the result from the first source.	4
VSHUFI64X2	Picks 128-bit blocks of quadwords from the two sources as an immediate selects, the lower half of the result from the first source.	4
VSHUFPD	Picks doubles from the two sources for each position within each 128-bit lane, as an immediate selects.	6
VSHUFPS	Picks singles from the two sources for each position within each 128-bit lane, as an immediate selects.	6
VSQRTPD	Computes the square root of packed doubles.	6
VSQRTPH	Computes the square root of packed half-precision values.	6
VSQRTPS	Computes the square root of packed singles.	6
VSQRTSD	Computes the square root of the low double of the second source; the other elements come from the first source.	2
VSQRTSH	Computes the square root of the low half-precision value of the second source; the other elements come from the first source.	2
VSQRTSS	Computes the square root of the low single of the second source; the other elements come from the first source.	2
VSUBPD	Subtracts packed doubles.	6
VSUBPH	Subtracts packed half-precision values.	6
VSUBPS	Subtracts packed singles.	6
VSUBSD	Subtracts the low doubles; the other elements come from the first source.	2
VSUBSH	Subtracts the low half-precision values; the other elements come from the first source.	2
VSUBSS	Subtracts the low singles; the other elements come from the first source.	2
VUCOMISD	Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception.	2
VUCOMISH	Compares the low half-precision values and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception.	2
VUCOMISS	Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception.	2
VUNPCKHPD	Interleaves the high doubles of each 128-bit lane of two sources.	6
VUNPCKHPS	Interleaves the high singles of each 128-bit lane of two sources.	6
VUNPCKLPD	Interleaves the low doubles of each 128-bit lane of two sources.	6
VUNPCKLPS	Interleaves the low singles of each 128-bit lane of two sources.	6
VXORPD	Computes the bitwise XOR of packed doubles.	6
VXORPS	Computes the bitwise XOR of packed singles.	6

CPUID and processors

XED splits AVX10.1 into 57 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AVX10.1. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.

ISA set	CPUID	Processors in XED
`AVX512BW_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512BW_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512BW_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512BW_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512BW_KOPD` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512BW_KOPQ` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512CD_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512CD + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[28]` AVX512CD `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512CD_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512CD + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[28]` AVX512CD `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512CD_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512CD `CPUID.(EAX=07H,ECX=0):EBX[28]` AVX512CD	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
`AVX512DQ_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512DQ_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512DQ_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512DQ_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512DQ_KOPB` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512DQ_KOPW` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512DQ_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512F_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512F_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
`AVX512F_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512F_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
`AVX512F_KOPW` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
`AVX512F_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
`AVX512_BF16_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_BF16 `CPUID.(EAX=07H,ECX=1):EAX[5]` AVX512_BF16	Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_BF16_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_BF16 `CPUID.(EAX=07H,ECX=1):EAX[5]` AVX512_BF16	Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_BF16_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_BF16 `CPUID.(EAX=07H,ECX=1):EAX[5]` AVX512_BF16	Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_BITALG_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_BITALG + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[12]` AVX512_BITALG `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_BITALG_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_BITALG + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[12]` AVX512_BITALG `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_BITALG_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_BITALG `CPUID.(EAX=07H,ECX=0):ECX[12]` AVX512_BITALG	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_FP16_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 + AVX512VL `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_FP16_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_FP16_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 + AVX512VL `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_FP16_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_FP16_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_GFNI_128` AVX10.1	AVX10.1 + GFNI `CPUID.(EAX=07H,ECX=0):ECX[8]` GFNI `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or GFNI + AVX512F + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[8]` GFNI `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_GFNI_256` AVX10.1	AVX10.1 + GFNI `CPUID.(EAX=07H,ECX=0):ECX[8]` GFNI `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or GFNI + AVX512F + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[8]` GFNI `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_GFNI_512` AVX10.1	AVX10.1 + GFNI `CPUID.(EAX=07H,ECX=0):ECX[8]` GFNI `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or GFNI + AVX512F `CPUID.(EAX=07H,ECX=0):ECX[8]` GFNI `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_IFMA_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512IFMA + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[21]` AVX512IFMA `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_IFMA_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512IFMA + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[21]` AVX512IFMA `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_IFMA_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512IFMA `CPUID.(EAX=07H,ECX=0):EBX[21]` AVX512IFMA	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VAES_128` AVX10.1	AVX10.1 + VAES `CPUID.(EAX=07H,ECX=0):ECX[9]` VAES `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or VAES + AES + AVX512F + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[9]` VAES `CPUID.01H:ECX[25]` AES `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VAES_256` AVX10.1	AVX10.1 + VAES `CPUID.(EAX=07H,ECX=0):ECX[9]` VAES `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or VAES + AES + AVX512F + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[9]` VAES `CPUID.01H:ECX[25]` AES `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VAES_512` AVX10.1	AVX10.1 + VAES `CPUID.(EAX=07H,ECX=0):ECX[9]` VAES `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or VAES + AES + AVX512F `CPUID.(EAX=07H,ECX=0):ECX[9]` VAES `CPUID.01H:ECX[25]` AES `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VBMI2_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_VBMI2 + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[6]` AVX512_VBMI2 `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VBMI2_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_VBMI2 + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[6]` AVX512_VBMI2 `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VBMI2_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_VBMI2 `CPUID.(EAX=07H,ECX=0):ECX[6]` AVX512_VBMI2	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VBMI_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512VBMI + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[1]` AVX512VBMI `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VBMI_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512VBMI + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[1]` AVX512VBMI `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VBMI_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512VBMI `CPUID.(EAX=07H,ECX=0):ECX[1]` AVX512VBMI	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VNNI_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_VNNI + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[11]` AVX512_VNNI `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VNNI_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_VNNI + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[11]` AVX512_VNNI `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VNNI_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_VNNI `CPUID.(EAX=07H,ECX=0):ECX[11]` AVX512_VNNI	Ice Lake (client), Tiger Lake, Nova Lake, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VPCLMULQDQ_128` AVX10.1	AVX10.1 + VPCLMULQDQ `CPUID.(EAX=07H,ECX=0):ECX[10]` VPCLMULQDQ `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or VPCLMULQDQ + PCLMULQDQ + AVX512F + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[10]` VPCLMULQDQ `CPUID.01H:ECX[1]` PCLMULQDQ `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VPCLMULQDQ_256` AVX10.1	AVX10.1 + VPCLMULQDQ `CPUID.(EAX=07H,ECX=0):ECX[10]` VPCLMULQDQ `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or VPCLMULQDQ + PCLMULQDQ + AVX512F + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[10]` VPCLMULQDQ `CPUID.01H:ECX[1]` PCLMULQDQ `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VPCLMULQDQ_512` AVX10.1	AVX10.1 + VPCLMULQDQ `CPUID.(EAX=07H,ECX=0):ECX[10]` VPCLMULQDQ `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or VPCLMULQDQ + PCLMULQDQ + AVX512F `CPUID.(EAX=07H,ECX=0):ECX[10]` VPCLMULQDQ `CPUID.01H:ECX[1]` PCLMULQDQ `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VPOPCNTDQ_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_VPOPCNTDQ + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[14]` AVX512_VPOPCNTDQ `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VPOPCNTDQ_256` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_VPOPCNTDQ + AVX512VL `CPUID.(EAX=07H,ECX=0):ECX[14]` AVX512_VPOPCNTDQ `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
`AVX512_VPOPCNTDQ_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_VPOPCNTDQ `CPUID.(EAX=07H,ECX=0):ECX[14]` AVX512_VPOPCNTDQ	Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Mill

Detection#

One vector length for all#

In this reference#

Instructions

CPUID and processors

Sources

Detection

One vector length for all

In this reference