AVX10.2 instruction set extension

AVX10.2 is the first AVX10 version with new instructions, and the one Intel’s specification calls the first fully featured version for both client and server processors. Most of it targets machine learning formats, media and language runtimes that need exact IEEE or saturating behavior.

What it adds

bfloat16 arithmetic. AVX512_BF16 only converted to bfloat16 and computed dot products. AVX10.2 adds the usual arithmetic on packed bfloat16: VADDBF16 and the other basic operations, fused multiply-add, compares, classification, reciprocal and square-root estimates, and scaling.
FP8 conversions. Conversions between half precision and the two 8-bit formats of the OCP OFP8 specification, E5M2 (called BF8 in the mnemonics) and E4M3 (HF8). Versions ending in S turn values too large for the format into its largest finite value rather than infinity or NaN, and the BIAS versions add a caller-chosen bias before truncating, which allows stochastic rounding. These conversions neither read nor update MXCSR.
Saturating conversions. Float-to-integer conversions such as VCVTTPS2DQS clamp out-of-range values and turn NaN into zero, as Rust’s float-to-integer casts and WebAssembly’s saturating truncations require. The older conversions return the “integer indefinite” value instead.
IEEE 754-2019 minimum and maximum. VMINMAXPS and its siblings implement the eight minimum and maximum operations of the standard.
Compares that set every relation. VCOMXSS and its siblings set the flags so that each relation needs one conditional jump.
More dot products. EVEX forms of the byte and word dot products of AVX-VNNI-INT8 and AVX-VNNI-INT16 (for example VPDPBSSD), and VDPPHPS for half precision.
Media and moves. VMPSADBW reaches 512 bits, and VMOVD and VMOVW gain register-to-register forms that zero the rest of the destination.

Detection

AVX10.2 is AVX10 (CPUID.(EAX=07H,ECX=1):EDX[19]) with version 2 or later in CPUID.(EAX=24H,ECX=0):EBX[7:0]. Revision 6.0 of the specification also lets the EVEX dot products and the FP8 and FP16 conversions be enumerated by a separate bit, AVX10_V1_AUX (CPUID.(EAX=24H,ECX=1):ECX[2]), for platforms that offer them without all of AVX10.2; on Intel processors the bit and AVX10.2 always go together. The tables list both requirements.

Revision 4.0 removed the embedded rounding forms of 256-bit instructions that earlier drafts had added; rounding control stays 512-bit and scalar only. XED’s chip model places AVX10.2 in Diamond Rapids and Nova Lake.

Instructions

Mnemonics with at least one form in AVX10.2. Each page lists all forms of the mnemonic, including those of other extensions.

Mnemonic	Summary	Forms
VADDBF16	Adds packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions.	6
VCMPBF16	Compares packed bfloat16 values with one of 32 predicates chosen by an immediate and writes the results to a mask register.	6
VCOMISBF16	Compares the low bfloat16 values of two registers and sets ZF, PF and CF as COMISS does, without floating-point exceptions.	2
VCOMXSD	Compares the low doubles and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation, unordered included; NaNs signal invalid.	2
VCOMXSH	Compares the low half-precision values and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation; NaNs signal invalid.	2
VCOMXSS	Compares the low singles and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation, unordered included; NaNs signal invalid.	2
VCVT2PH2BF8	Converts two vectors of half-precision values into one vector of E5M2 FP8 values, rounding to nearest even.	6
VCVT2PH2BF8S	Converts two vectors of half-precision values into one vector of E5M2 FP8 values, saturating values too large for FP8 to its largest normal.	6
VCVT2PH2HF8	Converts two vectors of half-precision values into one vector of E4M3 FP8 values, rounding to nearest even.	6
VCVT2PH2HF8S	Converts two vectors of half-precision values into one vector of E4M3 FP8 values, saturating values too large for FP8 to its largest normal.	6
VCVT2PS2PHX	Converts two vectors of single-precision values into one vector of half-precision values, rounding as MXCSR or the instruction selects.	6
VCVTBF162IBS	Converts packed bfloat16 values to signed bytes with saturation, rounding to nearest even, each result in the low byte of a zeroed 16-bit element.	6
VCVTBF162IUBS	Converts packed bfloat16 values to saturated unsigned bytes, rounding to nearest even, each in the low byte of a zeroed 16-bit element.	6
VCVTBIASPH2BF8	Converts packed half-precision values to E5M2 FP8, adding an 8-bit bias below the kept bits before truncating, which allows stochastic rounding.	6
VCVTBIASPH2BF8S	Converts packed half-precision values to E5M2 FP8 with an 8-bit rounding bias, saturating values too large for FP8 to its largest normal.	6
VCVTBIASPH2HF8	Converts packed half-precision values to E4M3 FP8, adding an 8-bit bias below the kept bits before truncating, which allows stochastic rounding.	6
VCVTBIASPH2HF8S	Converts packed half-precision values to E4M3 FP8 with an 8-bit rounding bias, saturating values too large for FP8 to its largest normal.	6
VCVTHF82PH	Converts packed E4M3 FP8 values to half precision, which is exact.	6
VCVTPH2BF8	Converts packed half-precision values to E5M2 FP8, rounding to nearest even.	6
VCVTPH2BF8S	Converts packed half-precision values to E5M2 FP8, saturating values too large for FP8 to its largest normal.	6
VCVTPH2HF8	Converts packed half-precision values to E4M3 FP8, rounding to nearest even.	6
VCVTPH2HF8S	Converts packed half-precision values to E4M3 FP8, saturating values too large for FP8 to its largest normal.	6
VCVTPH2IBS	Converts packed half-precision values to signed bytes with saturation, each result in the low byte of a zeroed 16-bit element.	6
VCVTPH2IUBS	Converts packed half-precision values to unsigned bytes with saturation, each result in the low byte of a zeroed 16-bit element.	6
VCVTPS2IBS	Converts packed single-precision values to signed bytes with saturation, each result in the low byte of a zeroed 32-bit element.	6
VCVTPS2IUBS	Converts packed single-precision values to unsigned bytes with saturation, each result in the low byte of a zeroed 32-bit element.	6
VCVTTBF162IBS	Converts packed bfloat16 values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element.	6
VCVTTBF162IUBS	Converts packed bfloat16 values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element.	6
VCVTTPD2DQS	Converts packed doubles to 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN.	6
VCVTTPD2QQS	Converts packed doubles to 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN.	6
VCVTTPD2UDQS	Converts packed doubles to unsigned 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN.	6
VCVTTPD2UQQS	Converts packed doubles to unsigned 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN.	6
VCVTTPH2IBS	Converts packed half-precision values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element.	6
VCVTTPH2IUBS	Converts packed half-precision values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element.	6
VCVTTPS2DQS	Converts packed singles to 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN.	6
VCVTTPS2IBS	Converts packed single-precision values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 32-bit element.	6
VCVTTPS2IUBS	Converts packed single-precision values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 32-bit element.	6
VCVTTPS2QQS	Converts packed singles to 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN.	6
VCVTTPS2UDQS	Converts packed singles to unsigned 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN.	6
VCVTTPS2UQQS	Converts packed singles to unsigned 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN.	6
VCVTTSD2SIS	Converts the low double to a signed 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN.	4
VCVTTSD2USIS	Converts the low double to an unsigned 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN.	4
VCVTTSS2SIS	Converts the low single to a signed 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN.	4
VCVTTSS2USIS	Converts the low single to an unsigned 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN.	4
VDIVBF16	Divides packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions.	6
VDPPHPS	Multiplies pairs of half-precision values and adds both products to the matching single-precision accumulator.	6
VFMADD132BF16	Fused multiply-add of packed bfloat16 values: first operand times third plus second, into the first.	6
VFMADD213BF16	Fused multiply-add of packed bfloat16 values: second operand times first plus third, into the first.	6
VFMADD231BF16	Fused multiply-add of packed bfloat16 values: second operand times third plus first, into the first.	6
VFMSUB132BF16	Fused multiply-subtract of packed bfloat16 values: first operand times third minus second, into the first.	6
VFMSUB213BF16	Fused multiply-subtract of packed bfloat16 values: second operand times first minus third, into the first.	6
VFMSUB231BF16	Fused multiply-subtract of packed bfloat16 values: second operand times third minus first, into the first.	6
VFNMADD132BF16	Fused negated multiply-add of packed bfloat16 values: minus first operand times third, plus second, into the first.	6
VFNMADD213BF16	Fused negated multiply-add of packed bfloat16 values: minus second operand times first, plus third, into the first.	6
VFNMADD231BF16	Fused negated multiply-add of packed bfloat16 values: minus second operand times third, plus first, into the first.	6
VFNMSUB132BF16	Fused negated multiply-subtract of packed bfloat16 values: minus first operand times third, minus second, into the first.	6
VFNMSUB213BF16	Fused negated multiply-subtract of packed bfloat16 values: minus second operand times first, minus third, into the first.	6
VFNMSUB231BF16	Fused negated multiply-subtract of packed bfloat16 values: minus second operand times third, minus first, into the first.	6
VFPCLASSBF16	Tests packed bfloat16 values for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register.	6
VGETEXPBF16	Extracts the unbiased exponent of each packed bfloat16 value as a bfloat16 number.	6
VGETMANTBF16	Extracts the normalized mantissa of each packed bfloat16 value, with the interval and sign handling chosen by an immediate.	6
VMAXBF16	Returns the larger of each pair of packed bfloat16 values, with the x86 convention of returning the second operand if either is NaN or both are zero.	6
VMINBF16	Returns the smaller of each pair of packed bfloat16 values, with the x86 convention of returning the second operand if either is NaN or both are zero.	6
VMINMAXBF16	Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed bfloat16 values, as an immediate selects, with sign control.	6
VMINMAXPD	Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed doubles, as an immediate selects, with sign control.	6
VMINMAXPH	Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed half-precision values, as an immediate selects, with sign control.	6
VMINMAXPS	Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed singles, as an immediate selects, with sign control.	6
VMINMAXSD	Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low doubles, as an immediate selects, with sign control.	2
VMINMAXSH	Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low half-precision values, as an immediate selects, with sign control.	2
VMINMAXSS	Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low singles, as an immediate selects, with sign control.	2
VMOVD	Moves 32 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form.	3
VMOVW	Moves 16 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form.	3
VMPSADBW	Computes, per 128-bit lane, word sums of absolute differences between a 4-byte block of the second source and eight sliding blocks of the first.	6
VMULBF16	Multiplies packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions.	6
VPDPBSSD	Multiplies signed bytes by signed bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator.	6
VPDPBSSDS	Multiplies signed bytes by signed bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator with signed saturation.	6
VPDPBSUD	Multiplies signed bytes of the first source by unsigned bytes of the second and adds each group of four products to a 32-bit accumulator.	6
VPDPBSUDS	Multiplies signed bytes of the first source by unsigned bytes of the second and adds each group of four products to a 32-bit accumulator, saturating.	6
VPDPBUUD	Multiplies unsigned bytes by unsigned bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator.	6
VPDPBUUDS	Multiplies unsigned bytes by unsigned bytes and adds each group of four products to the matching 32-bit accumulator with unsigned saturation.	6
VPDPWSUD	Multiplies signed words of the first source by unsigned words of the second and adds each pair of products to a 32-bit accumulator.	6
VPDPWSUDS	Multiplies signed words of the first source by unsigned words of the second and adds each pair of products to a 32-bit accumulator, saturating.	6
VPDPWUSD	Multiplies unsigned words of the first source by signed words of the second and adds each pair of products to a 32-bit accumulator.	6
VPDPWUSDS	Multiplies unsigned words of the first source by signed words of the second and adds each pair of products to a 32-bit accumulator, saturating.	6
VPDPWUUD	Multiplies unsigned words by unsigned words and adds each pair of products to the matching 32-bit accumulator.	6
VPDPWUUDS	Multiplies unsigned words by unsigned words and adds each pair of products to the matching 32-bit accumulator with unsigned saturation.	6
VRCPBF16	Approximates the reciprocal of each packed bfloat16 value with a relative error below 2^-8 + 2^-14.	6
VREDUCEBF16	Subtracts from each packed bfloat16 value its value rounded to the number of fraction bits an immediate gives, leaving the reduced argument.	6
VRNDSCALEBF16	Rounds each packed bfloat16 value to the number of fraction bits an immediate gives.	6
VRSQRTBF16	Approximates the reciprocal square root of each packed bfloat16 value with a relative error below 2^-8 + 2^-14.	6
VSCALEFBF16	Multiplies each packed bfloat16 value by 2 raised to the floor of the corresponding value of the second source.	6
VSQRTBF16	Computes the square root of each packed bfloat16 value, rounding to nearest, with denormals treated as zero and without floating-point exceptions.	6
VSUBBF16	Subtracts packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions.	6
VUCOMXSD	Compares the low double-precision values of two operands like VCOMXSD but signals an invalid exception only for signaling NaNs.	2
VUCOMXSH	Compares the low half-precision values of two operands like VCOMXSH but signals an invalid exception only for signaling NaNs.	2
VUCOMXSS	Compares the low single-precision values of two operands like VCOMXSS but signals an invalid exception only for signaling NaNs.	2

CPUID and processors

XED splits AVX10.2 into 35 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AVX10.2. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.

ISA set	CPUID	Processors in XED
`AVX10_2_BF16_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX10_2_BF16_256` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX10_2_BF16_512` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX10_2_BF16_SCALAR` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_COM_EF_SCALAR` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_FP16_CONVERT_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids
`AVX512_FP16_CONVERT_256` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids
`AVX512_FP16_CONVERT_512` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids
`AVX512_FP8_CONVERT_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids
`AVX512_FP8_CONVERT_256` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids
`AVX512_FP8_CONVERT_512` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids
`AVX512_MEDIAX_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_MEDIAX_256` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_MEDIAX_512` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_MINMAX_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_MINMAX_256` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_MINMAX_512` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_MINMAX_SCALAR` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_MOVZXC_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_SAT_CVT_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_SAT_CVT_256` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_SAT_CVT_512` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_SAT_CVT_DS_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_SAT_CVT_DS_256` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_SAT_CVT_DS_512` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_SAT_CVT_DS_SCALAR` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_VNNI_FP16_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_VNNI_FP16_256` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_VNNI_FP16_512` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids
`AVX512_VNNI_INT16_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids
`AVX512_VNNI_INT16_256` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids
`AVX512_VNNI_INT16_512` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids
`AVX512_VNNI_INT8_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids
`AVX512_VNNI_INT8_256` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids
`AVX512_VNNI_INT8_512` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version or AVX10_V1_AUX `CPUID.(EAX=24H,ECX=1):ECX[2]` AVX10_V1_AUX	Nova Lake, Diamond Rapids

What it adds#

Detection#

Instructions

CPUID and processors

Sources

What it adds

Detection