Vector (SSE, AVX and AVX10)
AVX10_V2_AUX
Conversions from single precision to FP8 and between FP8 and the 6- and 4-bit formats of the OCP microscaling specification, defined with ACE.
- CPUID
- AVX10 + AVX10_V2_AUX
CPUID.(EAX=07H,ECX=1):EDX[19]CPUID.(EAX=24H,ECX=1):ECX[3] - Instructions
- 21 mnemonics
- Processors
- None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
AVX10_V2_AUX is a group of vector conversions defined in the x86 Ecosystem Advisory Group’s ACE specification rather than by Intel’s AVX10 documents. It is enumerated by CPUID.(EAX=24H,ECX=1):ECX[3] and needs AVX10.
It fills the gaps around the OCP microscaling (MX) formats that ACE’s matrix instructions consume:
- conversions from single precision to FP8, with round-to-nearest, round-to-odd (VCVTROPS2HF8) and bias rounding, and back from FP8 to single precision;
- conversions between FP8 and the 6-bit (E2M3, E3M2) and 4-bit (E2M1) MX formats;
- VPMOVSSDB, which narrows dwords to bytes with symmetric signed saturation, and VUNPACKB, which expands packed narrow fields to bytes.
The ACE specification’s detection sequence for full ACE support requires this bit. XED’s chip model has the group only in a placeholder for future processors, so no processor is listed here.
Part of AVX10.3
The ACE v2 / AVX10.3 specification, a draft at version 0.9.2.4 (October 2026), makes every instruction of the group part of AVX10.3. A processor that reports AVX10 version 3 or later in CPUID.(EAX=24H,ECX=0):EBX[7:0] has them, and the draft’s detection sequence counts either that version or the ECX[3] bit. It also says that every processor with ACE sets the bit, including those that report AVX10.3. For the operation, encodings and exceptions of these instructions it still refers to the ACE v1 specification. The CPUID section below follows XED, which knows only the bit.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| VCVTBF42HF8 | Converts packed 4-bit E2M1 floating-point values to E4M3 FP8, which is exact. | 6 |
| VCVTBF62HF8 | Converts packed 6-bit E3M2 floating-point values to E4M3 FP8, which is exact. | 3 |
| VCVTBF82BF4S | Converts packed E5M2 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values. | 6 |
| VCVTBF82BF6S | Converts packed E5M2 FP8 values to the 6-bit E3M2 format, rounding to nearest even and saturating out-of-range values. | 3 |
| VCVTBF82PS | Converts packed E5M2 FP8 values to single precision, which is exact. | 6 |
| VCVTBIASPS2BF8 | Converts packed single-precision values to E5M2 FP8 with a rounding bias taken from another register, which allows stochastic rounding. | 6 |
| VCVTBIASPS2BF8S | Converts packed single-precision values to E5M2 FP8 with a rounding bias, saturating values too large for FP8 to its largest normal. | 6 |
| VCVTBIASPS2HF8 | Converts packed single-precision values to E4M3 FP8 with a rounding bias taken from another register, which allows stochastic rounding. | 6 |
| VCVTBIASPS2HF8S | Converts packed single-precision values to E4M3 FP8 with a rounding bias, saturating values too large for FP8 to its largest normal. | 6 |
| VCVTHF62HF8 | Converts packed 6-bit E2M3 floating-point values to E4M3 FP8, which is exact. | 3 |
| VCVTHF82BF4S | Converts packed E4M3 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values. | 6 |
| VCVTHF82HF6S | Converts packed E4M3 FP8 values to the 6-bit E2M3 format, rounding to nearest even and saturating out-of-range values. | 3 |
| VCVTHF82PS | Converts packed E4M3 FP8 values to single precision, which is exact. | 6 |
| VCVTPS2BF8 | Converts packed single-precision values to E5M2 FP8, rounding to nearest even. | 6 |
| VCVTPS2BF8S | Converts packed single-precision values to E5M2 FP8, saturating values too large for FP8 to its largest normal. | 6 |
| VCVTPS2HF8 | Converts packed single-precision values to E4M3 FP8, rounding to nearest even. | 6 |
| VCVTPS2HF8S | Converts packed single-precision values to E4M3 FP8, saturating values too large for FP8 to its largest normal. | 6 |
| VCVTROPS2HF8 | Converts packed single-precision values to E4M3 FP8, rounding to odd, which avoids double-rounding errors when the result is narrowed again. | 6 |
| VCVTROPS2HF8S | Converts packed single-precision values to E4M3 FP8, rounding to odd and saturating values too large for FP8 to its largest normal. | 6 |
| VPMOVSSDB | Narrows packed signed doublewords to bytes with symmetric saturation, to the range -127 to 127. | 6 |
| VUNPACKB | Unpacks tightly packed 2- to 7-bit fields into bytes, zero- or sign-extended, with the field size and start given by an immediate. | 6 |
CPUID and processors
XED splits AVX10_V2_AUX into 3 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors |
|---|---|---|
AVX10_V2_AUX_128 | AVX10_V2_AUX + AVX10 | None in XED’s chip model, which lists these instructions only under its placeholder for future processors. |
AVX10_V2_AUX_256 | Same as AVX10_V2_AUX_128 | None in XED’s chip model, which lists these instructions only under its placeholder for future processors. |
AVX10_V2_AUX_512 | Same as AVX10_V2_AUX_128 | None in XED’s chip model, which lists these instructions only under its placeholder for future processors. |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)
- x86 Ecosystem Advisory Group: ACE v2 / AVX10.3 Architecture Specification, version 0.9.2.4 (October 22, 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.