AVX10_V2_AUX instruction set extension

AVX10_V2_AUX is a group of vector conversions defined in the x86 Ecosystem Advisory Group’s ACE specification rather than by Intel’s AVX10 documents. It is enumerated by CPUID.(EAX=24H,ECX=1):ECX[3] and needs AVX10.

It fills the gaps around the OCP microscaling (MX) formats that ACE’s matrix instructions consume:

conversions from single precision to FP8, with round-to-nearest, round-to-odd (VCVTROPS2HF8) and bias rounding, and back from FP8 to single precision;
conversions between FP8 and the 6-bit (E2M3, E3M2) and 4-bit (E2M1) MX formats;
VPMOVSSDB, which narrows dwords to bytes with symmetric signed saturation, and VUNPACKB, which expands packed narrow fields to bytes.

The ACE specification’s detection sequence for full ACE support requires this bit. XED’s chip model has the group only in a placeholder for future processors, so no processor is listed here.

Instructions

Mnemonics with at least one form in AVX10_V2_AUX. Each page lists all forms of the mnemonic, including those of other extensions.

Mnemonic	Summary	Forms
VCVTBF42HF8	Converts packed 4-bit E2M1 floating-point values to E4M3 FP8, which is exact.	6
VCVTBF62HF8	Converts packed 6-bit E3M2 floating-point values to E4M3 FP8, which is exact.	3
VCVTBF82BF4S	Converts packed E5M2 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values.	6
VCVTBF82BF6S	Converts packed E5M2 FP8 values to the 6-bit E3M2 format, rounding to nearest even and saturating out-of-range values.	3
VCVTBF82PS	Converts packed E5M2 FP8 values to single precision, which is exact.	6
VCVTBIASPS2BF8	Converts packed single-precision values to E5M2 FP8 with a rounding bias taken from another register, which allows stochastic rounding.	6
VCVTBIASPS2BF8S	Converts packed single-precision values to E5M2 FP8 with a rounding bias, saturating values too large for FP8 to its largest normal.	6
VCVTBIASPS2HF8	Converts packed single-precision values to E4M3 FP8 with a rounding bias taken from another register, which allows stochastic rounding.	6
VCVTBIASPS2HF8S	Converts packed single-precision values to E4M3 FP8 with a rounding bias, saturating values too large for FP8 to its largest normal.	6
VCVTHF62HF8	Converts packed 6-bit E2M3 floating-point values to E4M3 FP8, which is exact.	3
VCVTHF82BF4S	Converts packed E4M3 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values.	6
VCVTHF82HF6S	Converts packed E4M3 FP8 values to the 6-bit E2M3 format, rounding to nearest even and saturating out-of-range values.	3
VCVTHF82PS	Converts packed E4M3 FP8 values to single precision, which is exact.	6
VCVTPS2BF8	Converts packed single-precision values to E5M2 FP8, rounding to nearest even.	6
VCVTPS2BF8S	Converts packed single-precision values to E5M2 FP8, saturating values too large for FP8 to its largest normal.	6
VCVTPS2HF8	Converts packed single-precision values to E4M3 FP8, rounding to nearest even.	6
VCVTPS2HF8S	Converts packed single-precision values to E4M3 FP8, saturating values too large for FP8 to its largest normal.	6
VCVTROPS2HF8	Converts packed single-precision values to E4M3 FP8, rounding to odd, which avoids double-rounding errors when the result is narrowed again.	6
VCVTROPS2HF8S	Converts packed single-precision values to E4M3 FP8, rounding to odd and saturating values too large for FP8 to its largest normal.	6
VPMOVSSDB	Narrows packed signed doublewords to bytes with symmetric saturation, to the range -127 to 127.	6
VUNPACKB	Unpacks tightly packed 2- to 7-bit fields into bytes, zero- or sign-extended, with the field size and start given by an immediate.	6

CPUID and processors

XED splits AVX10_V2_AUX into 3 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AVX10_V2_AUX. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.

ISA set	CPUID	Processors in XED
`AVX10_V2_AUX_128` AVX10_V2_AUX	AVX10_V2_AUX + AVX10 `CPUID.(EAX=24H,ECX=1):ECX[3]` AVX10_V2_AUX `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10	None yet: XED lists these instructions only under its placeholder for future processors.
`AVX10_V2_AUX_256` AVX10_V2_AUX	AVX10_V2_AUX + AVX10 `CPUID.(EAX=24H,ECX=1):ECX[3]` AVX10_V2_AUX `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10	None yet: XED lists these instructions only under its placeholder for future processors.
`AVX10_V2_AUX_512` AVX10_V2_AUX	AVX10_V2_AUX + AVX10 `CPUID.(EAX=24H,ECX=1):ECX[3]` AVX10_V2_AUX `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10	None yet: XED lists these instructions only under its placeholder for future processors.

Instructions

CPUID and processors

Sources