AVX2 instruction set extension

AVX2 extended the integer instructions of SSE2 to SSE4.2 to 256-bit YMM registers and added operations that SSE lacked: gathers that load elements from a vector of addresses (VPGATHERDD and relatives), permutes across the two 128-bit lanes (VPERMD, VPERM2I128), shifts by a count per element (VPSLLVD), broadcasts, and masked loads and stores (VPMASKMOVD). Most 256-bit integer instructions still work within each 128-bit lane, like two SSE instructions side by side. AVX2 is part of x86-64-v3, the level that RHEL 10 requires.

Instructions

Mnemonics with at least one form in AVX2. Each page lists all forms of the mnemonic, including those of other extensions.

Mnemonic	Summary	Forms
VBROADCASTI128	Loads 128 bits of integer data from memory into both halves of a YMM register; AVX2.	1
VBROADCASTSD	Copies one double from memory or an XMM register to every element of a vector.	1
VBROADCASTSS	Copies one single from memory or an XMM register to every element of a vector.	2
VEXTRACTI128	Copies the 128-bit half of a YMM register that an immediate selects to an XMM register or memory; AVX2.	2
VGATHERDPD	Loads doubles from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	2
VGATHERDPS	Loads singles from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	2
VGATHERQPD	Loads doubles from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	2
VGATHERQPS	Loads singles from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	2
VINSERTI128	Copies the first source to a YMM register and replaces the half an immediate selects with 128 bits of an XMM register or memory; AVX2.	2
VMOVNTDQA	Loads a vector from aligned memory with a non-temporal hint, which lets it read write-combining memory efficiently.	1
VMPSADBW	Computes, per 128-bit lane, word sums of absolute differences between a 4-byte block of the second source and eight sliding blocks of the first.	2
VPABSB	Computes the absolute value of packed signed bytes.	2
VPABSD	Computes the absolute value of packed signed doublewords.	2
VPABSW	Computes the absolute value of packed signed words.	2
VPACKSSDW	Narrows signed doublewords from two sources to words with signed saturation.	2
VPACKSSWB	Narrows signed words from two sources to bytes with signed saturation.	2
VPACKUSDW	Narrows signed doublewords from two sources to words with unsigned saturation.	2
VPACKUSWB	Narrows signed words from two sources to bytes with unsigned saturation.	2
VPADDB	Adds packed bytes, wrapping around on overflow.	2
VPADDD	Adds packed doublewords, wrapping around on overflow.	2
VPADDQ	Adds packed quadwords, wrapping around on overflow.	2
VPADDSB	Adds packed signed bytes with signed saturation.	2
VPADDSW	Adds packed signed words with signed saturation.	2
VPADDUSB	Adds packed unsigned bytes with unsigned saturation.	2
VPADDUSW	Adds packed unsigned words with unsigned saturation.	2
VPADDW	Adds packed words, wrapping around on overflow.	2
VPALIGNR	Concatenates two sources in each 128-bit lane and extracts 16 bytes starting at a byte offset given by an immediate.	2
VPAND	Computes the bitwise AND of two XMM or YMM sources into a separate destination (YMM with AVX2).	2
VPANDN	Computes the bitwise AND of the inverted first source with the second, in XMM or YMM registers (YMM with AVX2).	2
VPAVGB	Computes the rounded average of packed unsigned bytes.	2
VPAVGW	Computes the rounded average of packed unsigned words.	2
VPBLENDD	Picks each doubleword from the first or the second source, as a bit of an immediate says; AVX2.	4
VPBLENDVB	Picks each byte from the first or the second source by the top bit of the matching byte of a fourth register operand.	2
VPBLENDW	Picks each word from the first or the second source by a bit of an immediate, the same eight bits for each 128-bit lane.	2
VPBROADCASTB	Copies one byte from a register or memory to every byte of a vector.	4
VPBROADCASTD	Copies one doubleword from a register or memory to every doubleword of a vector.	4
VPBROADCASTQ	Copies one quadword from a register or memory to every quadword of a vector.	4
VPBROADCASTW	Copies one word from a register or memory to every word of a vector.	4
VPCMPEQB	Compares packed bytes for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPEQD	Compares packed doublewords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPEQQ	Compares packed quadwords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPEQW	Compares packed words for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPGTB	Tests packed signed bytes for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPGTD	Tests packed signed doublewords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPGTQ	Tests packed signed quadwords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPCMPGTW	Tests packed signed words for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.	2
VPERM2I128	Builds each 128-bit half of a YMM result from either half of two integer sources, or zero, as an immediate selects; AVX2.	2
VPERMD	Rearranges the doublewords of a vector across the whole register using an index vector.	2
VPERMPD	Rearranges doubles across the whole register, controlled by an immediate or by an index vector.	2
VPERMPS	Rearranges singles across the whole register using an index vector.	2
VPERMQ	Rearranges quadwords across the whole register, controlled by an immediate or by an index vector.	2
VPGATHERDD	Loads doublewords from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	2
VPGATHERDQ	Loads quadwords from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.	2
VPGATHERQD	Loads doublewords from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	2
VPGATHERQQ	Loads quadwords from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.	2
VPHADDD	Adds adjacent pairs of doublewords within each 128-bit lane of two sources, the first source's sums going low in the lane.	2
VPHADDSW	Adds adjacent pairs of signed words within each 128-bit lane with signed saturation, the first source's sums going low.	2
VPHADDW	Adds adjacent pairs of words within each 128-bit lane of two sources, the first source's sums going low in the lane.	2
VPHSUBD	Subtracts the odd doubleword from the even one in adjacent pairs within each 128-bit lane of two sources.	2
VPHSUBSW	Subtracts the odd signed word from the even one in adjacent pairs within each 128-bit lane, with signed saturation.	2
VPHSUBW	Subtracts the odd word from the even one in adjacent pairs within each 128-bit lane of two sources.	2
VPMADDUBSW	Multiplies unsigned bytes of the first source by signed bytes of the second and adds adjacent products into words with signed saturation.	2
VPMADDWD	Multiplies signed words and adds adjacent products into doublewords.	2
VPMASKMOVD	Loads or stores packed doublewords only where the top bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault.	4
VPMASKMOVQ	Loads or stores packed quadwords only where the top bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault.	4
VPMAXSB	Returns the larger of each pair of signed bytes.	2
VPMAXSD	Returns the larger of each pair of signed doublewords.	2
VPMAXSW	Returns the larger of each pair of signed words.	2
VPMAXUB	Returns the larger of each pair of unsigned bytes.	2
VPMAXUD	Returns the larger of each pair of unsigned doublewords.	2
VPMAXUW	Returns the larger of each pair of unsigned words.	2
VPMINSB	Returns the smaller of each pair of signed bytes.	2
VPMINSD	Returns the smaller of each pair of signed doublewords.	2
VPMINSW	Returns the smaller of each pair of signed words.	2
VPMINUB	Returns the smaller of each pair of unsigned bytes.	2
VPMINUD	Returns the smaller of each pair of unsigned doublewords.	2
VPMINUW	Returns the smaller of each pair of unsigned words.	2
VPMOVMSKB	Copies the top bit of each byte of an XMM or YMM register into the low bits of a general-purpose register.	1
VPMOVSXBD	Sign-extends packed bytes to doublewords.	2
VPMOVSXBQ	Sign-extends packed bytes to quadwords.	2
VPMOVSXBW	Sign-extends packed bytes to words.	2
VPMOVSXDQ	Sign-extends packed doublewords to quadwords.	2
VPMOVSXWD	Sign-extends packed words to doublewords.	2
VPMOVSXWQ	Sign-extends packed words to quadwords.	2
VPMOVZXBD	Zero-extends packed bytes to doublewords.	2
VPMOVZXBQ	Zero-extends packed bytes to quadwords.	2
VPMOVZXBW	Zero-extends packed bytes to words.	2
VPMOVZXDQ	Zero-extends packed doublewords to quadwords.	2
VPMOVZXWD	Zero-extends packed words to doublewords.	2
VPMOVZXWQ	Zero-extends packed words to quadwords.	2
VPMULDQ	Multiplies the signed low doublewords of each quadword into 64-bit products.	2
VPMULHRSW	Multiplies packed signed words as Q15 fixed-point numbers, rounding each product to a Q15 result.	2
VPMULHUW	Multiplies unsigned words and keeps the high 16 bits of each product.	2
VPMULHW	Multiplies signed words and keeps the high 16 bits of each product.	2
VPMULLD	Multiplies packed doublewords and keeps the low 32 bits of each product.	2
VPMULLW	Multiplies packed words and keeps the low 16 bits of each product.	2
VPMULUDQ	Multiplies the unsigned low doublewords of each quadword into 64-bit products.	2
VPOR	Computes the bitwise OR of two XMM or YMM sources into a separate destination (YMM with AVX2).	2
VPSADBW	Sums the absolute differences of unsigned bytes over each group of eight, giving one 16-bit sum per quadword.	2
VPSHUFB	Rearranges bytes within each 128-bit lane using an index byte per result, which zeroes the byte when its top bit is set.	2
VPSHUFD	Rearranges doublewords within each 128-bit lane as an immediate selects.	2
VPSHUFHW	Rearranges the upper four words of each 128-bit lane as an immediate selects.	2
VPSHUFLW	Rearranges the lower four words of each 128-bit lane as an immediate selects.	2
VPSIGNB	Negates, zeroes or keeps each signed byte of the first source as the matching byte of the second is negative, zero or positive.	2
VPSIGND	Negates, zeroes or keeps each doubleword of the first source as the matching one of the second is negative, zero or positive.	2
VPSIGNW	Negates, zeroes or keeps each signed word of the first source as the matching word of the second is negative, zero or positive.	2
VPSLLD	Shifts doublewords left by one count from a register or an immediate.	3
VPSLLDQ	Shifts each 128-bit lane left by a number of bytes given by an immediate.	1
VPSLLQ	Shifts quadwords left by one count from a register or an immediate.	3
VPSLLVD	Shifts each doubleword left by the count in the matching element of the second source.	4
VPSLLVQ	Shifts each quadword left by the count in the matching element of the second source.	4
VPSLLW	Shifts words left by one count from a register or an immediate.	3
VPSRAD	Shifts doublewords right arithmetically by one count from a register or an immediate.	3
VPSRAVD	Shifts each doubleword right arithmetically by the count in the matching element of the second source.	4
VPSRAW	Shifts words right arithmetically by one count from a register or an immediate.	3
VPSRLD	Shifts doublewords right logically by one count from a register or an immediate.	3
VPSRLDQ	Shifts each 128-bit lane right by a number of bytes given by an immediate.	1
VPSRLQ	Shifts quadwords right logically by one count from a register or an immediate.	3
VPSRLVD	Shifts each doubleword right logically by the count in the matching element of the second source.	4
VPSRLVQ	Shifts each quadword right logically by the count in the matching element of the second source.	4
VPSRLW	Shifts words right logically by one count from a register or an immediate.	3
VPSUBB	Subtracts packed bytes, wrapping around on overflow.	2
VPSUBD	Subtracts packed doublewords, wrapping around on overflow.	2
VPSUBQ	Subtracts packed quadwords, wrapping around on overflow.	2
VPSUBSB	Subtracts packed signed bytes with signed saturation.	2
VPSUBSW	Subtracts packed signed words with signed saturation.	2
VPSUBUSB	Subtracts packed unsigned bytes with unsigned saturation.	2
VPSUBUSW	Subtracts packed unsigned words with unsigned saturation.	2
VPSUBW	Subtracts packed words, wrapping around on overflow.	2
VPUNPCKHBW	Interleaves the high bytes of each 128-bit lane of two sources.	2
VPUNPCKHDQ	Interleaves the high doublewords of each 128-bit lane of two sources.	2
VPUNPCKHQDQ	Interleaves the high quadwords of each 128-bit lane of two sources.	2
VPUNPCKHWD	Interleaves the high words of each 128-bit lane of two sources.	2
VPUNPCKLBW	Interleaves the low bytes of each 128-bit lane of two sources.	2
VPUNPCKLDQ	Interleaves the low doublewords of each 128-bit lane of two sources.	2
VPUNPCKLQDQ	Interleaves the low quadwords of each 128-bit lane of two sources.	2
VPUNPCKLWD	Interleaves the low words of each 128-bit lane of two sources.	2
VPXOR	Computes the bitwise XOR of two XMM or YMM sources into a separate destination (YMM with AVX2).	2

CPUID and processors

XED splits AVX2 into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AVX2. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX2GATHER` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Instructions

CPUID and processors

Sources