CPUID
AVX512_4FMAPS
CPUID.(EAX=07H,ECX=0):EDX[3]
Instructions
4 mnemonics
Processors
Knights Mill

Instructions

Mnemonics with at least one form in AVX512_4FMAPS. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
V4FMADDPSPerforms four fused multiply-adds of packed singles in a row, each with the next of four ZMM registers and the next single from memory.1
V4FMADDSSPerforms four scalar fused multiply-adds of singles in a row, with the low singles of four consecutive registers and four from memory.1
V4FNMADDPSPerforms four fused negated multiply-adds of packed singles in a row, with four consecutive ZMM registers and four singles from memory.1
V4FNMADDSSPerforms four scalar fused negated multiply-adds of singles in a row, with four consecutive registers and four singles from memory.1

CPUID and processors

XED splits AVX512_4FMAPS into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AVX512_4FMAPS. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512_4FMAPS_512

AVX512_4FMAPS
CPUID.(EAX=07H,ECX=0):EDX[3] AVX512_4FMAPS

Knights Mill
AVX512_4FMAPS_SCALAR
Same as AVX512_4FMAPS_512Same as AVX512_4FMAPS_512

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.