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Vector (SSE, AVX and AVX10)

AVX512_4VNNIW instructions (Knights Mill)

AVX512_4VNNIW adds four dot products of signed words to doublewords in one instruction, with four consecutive ZMM registers and memory.

Only Knights Mill, the last Xeon Phi processor, has this instruction; no other Intel processor supports it.

CPUID
AVX512_4VNNIW
CPUID.(EAX=07H,ECX=0):EDX[2]
Instructions
2 mnemonics
Processors
Knights Mill

Instructions

Mnemonics with at least one form in AVX512_4VNNIW. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
VP4DPWSSDAdds four dot products of signed word pairs in a row to doublewords, with four consecutive ZMM registers and memory.1
VP4DPWSSDSAdds four dot products of signed word pairs in a row to doublewords with signed saturation, with four consecutive ZMM registers.1

CPUID and processors

XED splits AVX512_4VNNIW into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AVX512_4VNNIW. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512_4VNNIW_512

AVX512_4VNNIW
CPUID.(EAX=07H,ECX=0):EDX[2] AVX512_4VNNIW

Knights Mill

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.