x86-64.net

Vector (SSE, AVX and AVX10)

AVX512-VP2INTERSECT

AVX512-VP2INTERSECT finds the elements that two vectors of doublewords or quadwords have in common and writes the answer as a pair of masks.

CPUID
AVX512_VP2INTERSECT
CPUID.(EAX=07H,ECX=0):EDX[8]
Instructions
2 mnemonics
Processors
Tiger Lake, Zen 5, Zen 6 (from the CPU data, which follows GCC)
Linux flag
avx512_vp2intersect

VP2INTERSECTD and VP2INTERSECTQ compare every element of the first source with every element of the second. They write two masks into an even-odd pair of mask registers, such as k2 and k3: the first marks the elements of the first source that occur in the second, the second those of the second source that occur in the first.

AVX512-VP2INTERSECT is the one AVX-512 subset that neither AVX10 nor the Xeon Phi processors include. Intel’s reference names Tiger Lake as the only Intel processor with it; among AMD processors Zen 5 and the announced Zen 6 have it, as GCC’s -march=znver5 and -march=znver6 say. Clang’s intrinsics for it, such as _mm512_2intersect_epi32, store the two masks through pointers.

Instructions

Mnemonics with at least one form in AVX512-VP2INTERSECT. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
VP2INTERSECTDCompares every doubleword of one vector with every one of another and marks the elements that have a match in a pair of mask registers.6
VP2INTERSECTQCompares every quadword of one vector with every one of another and marks the elements that have a match in a pair of mask registers.6

CPUID and processors

XED splits AVX512-VP2INTERSECT into 3 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AVX512-VP2INTERSECT. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512_VP2INTERSECT_128

AVX512_VP2INTERSECT + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[8] AVX512_VP2INTERSECT
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Tiger Lake, Zen 5, Zen 6
AVX512_VP2INTERSECT_256

AVX512_VP2INTERSECT + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[8] AVX512_VP2INTERSECT
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Tiger Lake, Zen 5, Zen 6
AVX512_VP2INTERSECT_512

AVX512_VP2INTERSECT
CPUID.(EAX=07H,ECX=0):EDX[8] AVX512_VP2INTERSECT

Tiger Lake, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.