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Vector (SSE, AVX and AVX10)

AVX512ER instructions (Xeon Phi)

AVX512ER, the exponential and reciprocal instructions of the Xeon Phi processors, approximates 2^x, 1/x and 1/sqrt(x) in ZMM registers to within 2^-23 or 2^-28.

Only the Xeon Phi processors Knights Landing and Knights Mill have this instruction; no other Intel processor supports it.

CPUID
AVX512ER
CPUID.(EAX=07H,ECX=0):EBX[27]
Instructions
10 mnemonics
Processors
Knights Landing, Knights Mill

The Xeon Phi processors Knights Landing (Xeon Phi x200, 2016) and Knights Mill (2017) implemented AVX-512 Foundation and CD, and extensions of their own that no other Intel processor has: AVX512ER, AVX512PF and PREFETCHWT1, and on Knights Mill AVX512_4FMAPS and AVX512_4VNNIW. Intel’s manual describes them in a chapter of their own, and Clang 23 has no intrinsics for them. Their approximations are more precise than those of AVX-512 Foundation: VRCP28PS and VRSQRT28PS come within 2^-28 of the result where VRCP14PS comes within 2^-14, and VEXP2PS approximates 2^x directly.

Knights Corner, the Xeon Phi coprocessor before Knights Landing, had a 512-bit vector instruction set of its own with a different prefix, MVEX. XED does not decode it, so neither does this reference.

Instructions

Mnemonics with at least one form in AVX512ER. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
VEXP2PDApproximates 2 to the power of each packed double of a ZMM register, with a relative error below 2^-23.2
VEXP2PSApproximates 2 to the power of each packed single of a ZMM register, with a relative error below 2^-23.2
VRCP28PDApproximates the reciprocals of the packed doubles of a ZMM register, with a relative error below 2^-28.2
VRCP28PSApproximates the reciprocals of the packed singles of a ZMM register to within 2^-28, then rounds them to single precision.2
VRCP28SDApproximates the reciprocal of the low double to within 2^-28; the upper half comes from the first source.2
VRCP28SSApproximates the reciprocal of the low single to within 2^-28 before rounding; the rest comes from the first source.2
VRSQRT28PDApproximates the reciprocal square roots of the packed doubles of a ZMM register, with a relative error below 2^-28.2
VRSQRT28PSApproximates the reciprocal square roots of packed singles to within 2^-28, then rounds them to single precision.2
VRSQRT28SDApproximates the reciprocal square root of the low double to within 2^-28; the upper half comes from the first source.2
VRSQRT28SSApproximates the reciprocal square root of the low single to within 2^-28 before rounding; the rest comes from the first source.2

CPUID and processors

XED splits AVX512ER into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of AVX512ER. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512ER_512

AVX512ER
CPUID.(EAX=07H,ECX=0):EBX[27] AVX512ER

Knights Landing, Knights Mill
AVX512ER_SCALAR
Same as AVX512ER_512Same as AVX512ER_512

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  3. Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual (327364-001, September 2012)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.