Vector (SSE, AVX and AVX10)
AVX512PF instructions (Xeon Phi)
AVX512PF, the gather and scatter prefetches of the Xeon Phi processors, brings the elements that a vector of indices addresses into the first- or second-level cache ahead of a gather or scatter.
Only the Xeon Phi processors Knights Landing and Knights Mill have this instruction; no other Intel processor supports it.
- CPUID
- AVX512PF
CPUID.(EAX=07H,ECX=0):EBX[26] - Instructions
- 16 mnemonics
- Processors
- Knights Landing, Knights Mill
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| VGATHERPF0DPD | Prefetches the doubles that a vector of doubleword indices addresses into the first-level cache, under a mask. | 1 |
| VGATHERPF0DPS | Prefetches the singles that a vector of doubleword indices addresses into the first-level cache, under a mask. | 1 |
| VGATHERPF0QPD | Prefetches the doubles that a vector of quadword indices addresses into the first-level cache, under a mask. | 1 |
| VGATHERPF0QPS | Prefetches the singles that a vector of quadword indices addresses into the first-level cache, under a mask. | 1 |
| VGATHERPF1DPD | Prefetches the doubles that a vector of doubleword indices addresses into the second-level cache, under a mask. | 1 |
| VGATHERPF1DPS | Prefetches the singles that a vector of doubleword indices addresses into the second-level cache, under a mask. | 1 |
| VGATHERPF1QPD | Prefetches the doubles that a vector of quadword indices addresses into the second-level cache, under a mask. | 1 |
| VGATHERPF1QPS | Prefetches the singles that a vector of quadword indices addresses into the second-level cache, under a mask. | 1 |
| VSCATTERPF0DPD | Prefetches, with intent to write, the doubles that a vector of doubleword indices addresses into the first-level cache. | 1 |
| VSCATTERPF0DPS | Prefetches, with intent to write, the singles that a vector of doubleword indices addresses into the first-level cache. | 1 |
| VSCATTERPF0QPD | Prefetches, with intent to write, the doubles that a vector of quadword indices addresses into the first-level cache. | 1 |
| VSCATTERPF0QPS | Prefetches, with intent to write, the singles that a vector of quadword indices addresses into the first-level cache. | 1 |
| VSCATTERPF1DPD | Prefetches, with intent to write, the doubles that a vector of doubleword indices addresses into the second-level cache. | 1 |
| VSCATTERPF1DPS | Prefetches, with intent to write, the singles that a vector of doubleword indices addresses into the second-level cache. | 1 |
| VSCATTERPF1QPD | Prefetches, with intent to write, the doubles that a vector of quadword indices addresses into the second-level cache. | 1 |
| VSCATTERPF1QPS | Prefetches, with intent to write, the singles that a vector of quadword indices addresses into the second-level cache. | 1 |
CPUID and processors
XED splits AVX512PF into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors |
|---|---|---|
AVX512PF_512 | AVX512PF | Knights Landing, Knights Mill |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.