x86-64.net

General-purpose

BMI1

The first Bit Manipulation Instructions: ANDN, BEXTR, BLSI, BLSMSK, BLSR and TZCNT, which combine, extract, isolate and count bits in one VEX-encoded instruction each (TZCNT is a legacy encoding).

CPUID
BMI1
CPUID.(EAX=07H,ECX=0):EBX[3]
Instructions
6 mnemonics
Processors
Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill
Linux flag
bmi1

BMI1 adds six integer instructions that replace short sequences:

  • ANDN computes NOT of one source AND the other, into a separate destination.
  • BEXTR extracts a field of bits given by a start and a length.
  • BLSI, BLSMSK and BLSR isolate the lowest set bit, make a mask up to it, or clear it: x & -x, x ^ (x - 1) and x & (x - 1).
  • TZCNT counts trailing zero bits and returns the operand size for zero, where BSF leaves its destination unchanged.

All but TZCNT are VEX-encoded and work on general-purpose registers. TZCNT is BSF with an F3 prefix, so on older processors the same bytes run BSF, which gives the same count for any non-zero operand. BMI1 came with AMD’s Piledriver and Jaguar and Intel’s Haswell, and is part of x86-64-v3.

Instructions

Mnemonics with at least one form in BMI1. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
ANDNComputes the bitwise AND of the inverted first source with the second source into a separate destination; APX adds a form that leaves the flags unchanged.4
BEXTRExtracts a bit field whose start and length come from a second register; APX adds a form that leaves the flags unchanged.4
BLSIIsolates the lowest set bit of the source, clearing all others; APX adds a form that leaves the flags unchanged.4
BLSMSKSets all bits up to and including the lowest set bit of the source and clears the rest; APX adds a form that leaves the flags unchanged.4
BLSRClears the lowest set bit of the source; APX adds a form that leaves the flags unchanged.4
TZCNTCounts the trailing zero bits of an operand; APX adds a form that leaves the flags unchanged.2

CPUID and processors

XED splits BMI1 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of BMI1. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
BMI1

BMI1
CPUID.(EAX=07H,ECX=0):EBX[3] BMI1

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill

Note: XED's Piledriver adds TBM and FMA to Bulldozer but not BMI1, and its Zen chips inherit that gap; GCC's -march=bdver2 and -march=znver1 and later include BMI1.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.