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Memory, caches and atomics

CLDEMOTE

CLDEMOTE hints that a cache line should move from the core's own caches to a shared level, so that another core can read it sooner.

CPUID
CLDEMOTE
CPUID.(EAX=07H,ECX=0):ECX[25]
Instructions
1 mnemonic
Processors
Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Tremont, Snow Ridge, Sierra Forest, Clearwater Forest

When one core writes data that another core will read, the line sits modified in the writer’s private caches, and the reader’s access has to fetch it from there. CLDEMOTE hints that the line should move to a cache level farther from the core, such as a shared L3, where the other core finds it sooner. It changes no architectural state, and processors without it execute the encoding as a NOP, so software can use it unconditionally.

Instructions

Mnemonics with at least one form in CLDEMOTE. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CLDEMOTEHints that the cache line holding a byte of memory should move from the core's caches to a more distant level, where other cores reach it sooner.1

CPUID and processors

XED splits CLDEMOTE into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of CLDEMOTE. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
CLDEMOTE

CLDEMOTE
CPUID.(EAX=07H,ECX=0):ECX[25] CLDEMOTE

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Tremont, Snow Ridge, Sierra Forest, Clearwater Forest

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.