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Memory, caches and atomics

CLFLUSH

CLFLUSH writes a cache line back to memory and removes it from every cache in the system.

CPUID
CLFSH
CPUID.01H:EDX[19]
Instructions
1 mnemonic
Processors
Every x86-64 processor in XED’s model

CLFLUSH writes the cache line holding its memory operand back to memory if it was modified and removes it from every cache in the coherence domain. Drivers use it for memory that devices access without snooping the caches, and code for persistent memory to push stores out of the caches.

CLFLUSH is ordered with writes, locked instructions, fences and other CLFLUSHes, which makes flushing many lines slow; CLFLUSHOPT and CLWB relax that. The line size is in CPUID.01H:EBX[15:8], in units of 8 bytes, and the feature bit is called CLFSH.

Instructions

Mnemonics with at least one form in CLFLUSH. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CLFLUSHWrites back and invalidates the cache line holding a byte of memory in every cache of the coherence domain, ordered with writes and other CLFLUSHes.1

CPUID and processors

XED splits CLFLUSH into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of CLFLUSH. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
CLFSH

CLFSH
CPUID.01H:EDX[19] CLFSH

Every x86-64 processor in XED’s model

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.