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Memory, caches and atomics

CLFLUSHOPT

CLFLUSHOPT evicts a cache line like CLFLUSH but with weaker ordering, so that the flushes of many lines can overlap.

CPUID
CLFLUSHOPT
CPUID.(EAX=07H,ECX=0):EBX[23]
Instructions
1 mnemonic
Processors
Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen, Zen+, Zen 2

CLFLUSHOPT flushes a cache line as CLFLUSH does, but is ordered only with fences, locked instructions and older writes to the same line, not with other flushes. Flushes of different lines can therefore overlap, and a loop that flushes a large buffer runs faster. Software that needs them done before it goes on puts an SFENCE after them.

Instructions

Mnemonics with at least one form in CLFLUSHOPT. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CLFLUSHOPTWrites back and invalidates the cache line holding a byte of memory like CLFLUSH, but unordered with flushes of other lines, so several can overlap.1

CPUID and processors

XED splits CLFLUSHOPT into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of CLFLUSHOPT. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
CLFLUSHOPT

CLFLUSHOPT
CPUID.(EAX=07H,ECX=0):EBX[23] CLFLUSHOPT

Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen, Zen+, Zen 2

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.