x86-64.net

Memory, caches and atomics

CLWB

CLWB writes a modified cache line back to memory without necessarily evicting it, which makes stores to persistent memory durable at less cost than a flush.

CPUID
CLWB
CPUID.(EAX=07H,ECX=0):EBX[24]
Instructions
1 mnemonic
Processors
Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Tremont, Snow Ridge, Sierra Forest, Clearwater Forest, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
Linux flag
clwb

CLWB writes a modified cache line back to memory but, unlike the flushes, may keep it in the cache in an unmodified state, so the next access can still hit. That suits persistent memory, where software writes data back to make it durable and often reads it again soon. Like CLFLUSHOPT, it is not ordered with other flushes and write-backs, and an SFENCE orders it.

Instructions

Mnemonics with at least one form in CLWB. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CLWBWrites the cache line holding a byte of memory back if it was modified and may keep it cached, for example to make stores to persistent memory durable.1

CPUID and processors

XED splits CLWB into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of CLWB. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
CLWB

CLWB
CPUID.(EAX=07H,ECX=0):EBX[24] CLWB

Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Tremont, Snow Ridge, Sierra Forest, Clearwater Forest, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.