x86-64.net

Memory, caches and atomics

CLZERO

CLZERO zeroes a whole cache line with one instruction.

An AMD extension: Intel processors do not have this instruction.

CPUID
CLZERO
CPUID.80000008H:EBX[0]
Instructions
1 mnemonic
Processors
Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
Linux flag
clzero

Instructions

Mnemonics with at least one form in CLZERO. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CLZEROWrites zeros to the whole cache line that contains the address in rAX.1

CPUID and processors

XED splits CLZERO into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of CLZERO. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
CLZERO

CLZERO
CPUID.80000008H:EBX[0] CLZERO

Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.38, July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.