CPUID
CMOV
CPUID.01H:EDX[15]
Instructions
1 mnemonic
Processors
Every x86-64 processor in XED’s model
Linux flag
cmov

CMOVcc reads its source, a register or memory, and writes it to the destination register only if the condition holds; the conditions are those of Jcc and SETcc. Compilers use it to choose between two values without a branch that the processor might mispredict.

Two details differ from a branch around a MOV. The source is read even when the condition fails, so a CMOV from an invalid address faults either way. And with a 32-bit operand size in 64-bit mode the upper half of the destination is cleared even when nothing is moved. APX’s CFCMOVcc suppresses the memory access, and its faults, when the condition is false.

CMOV came with the Pentium Pro and is part of the x86-64 baseline.

Instructions

Mnemonics with at least one form in CMOV. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CMOVccCopies the source to a register if a condition on the flags holds; APX adds a three-operand form that picks one of two sources.2

CPUID and processors

XED splits CMOV into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of CMOV. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
CMOV

CMOV
CPUID.01H:EDX[15] CMOV

Every x86-64 processor in XED’s model

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.