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Memory, caches and atomics

CMPccXADD

Atomic compare and add: compares a value in memory with a register and, if the condition holds, adds another register to memory, returning the old value either way.

CPUID
CMPCCXADD
CPUID.(EAX=07H,ECX=1):EAX[7]
Instructions
1 mnemonic
Processors
Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Sierra Forest, Clearwater Forest

CMPccXADD adds one atomic read-modify-write instruction to x86: compare a memory value with a register and add another register to memory only if a condition holds. See CMPccXADD for how it works. All 16 condition codes exist, for 32- and 64-bit operands. The forms are VEX-encoded and exist only in 64-bit mode; APX adds EVEX forms that reach R16 to R31.

Instructions

Mnemonics with at least one form in CMPccXADD. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CMPccXADDAtomically compares memory with a register, adds a second register to memory if the condition holds, and returns the old value in the first.2

CPUID and processors

XED splits CMPccXADD into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of CMPccXADD. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
CMPCCXADD

CMPCCXADD
CPUID.(EAX=07H,ECX=1):EAX[7] CMPCCXADD

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Sierra Forest, Clearwater Forest

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.