x86-64.net

Memory, caches and atomics

CMPXCHG16B

CMPXCHG16B compares and exchanges 16 bytes of memory atomically, for lock-free structures that update a pointer and a counter together.

CPUID
CMPXCHG16B
CPUID.01H:ECX[13]
Instructions
1 mnemonic
Processors
Every x86-64 processor in XED’s model and Zen 3 to Zen 6
Linux flag
cx16

CMPXCHG16B compares RDX:RAX with 16 bytes of memory and, if they are equal, stores RCX:RBX there; otherwise it loads the memory into RDX:RAX. With a LOCK prefix it does all this atomically. The operand must be aligned to 16 bytes.

Lock-free data structures use it to update two words at once, such as a pointer and a counter that changes with every update, which defeats the ABA problem of a plain compare-and-exchange. It is the 64-bit counterpart of CMPXCHG8B. Some early x86-64 processors, such as AMD’s K8, lack it, so it has its own CPUID bit, CPUID.01H:ECX[13]; it is part of x86-64-v2.

Instructions

Mnemonics with at least one form in CMPXCHG16B. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CMPXCHG16BCompares RDX:RAX with 16 aligned bytes of memory: if equal, stores RCX:RBX there and sets ZF, else loads them into RDX:RAX; atomic with LOCK.2

CPUID and processors

XED splits CMPXCHG16B into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of CMPXCHG16B. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
CMPXCHG16B

CMPXCHG16B
CPUID.01H:ECX[13] CMPXCHG16B

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.