CMPXCHG16B instruction set extension

CMPXCHG16B compares RDX:RAX with 16 bytes of memory and, if they are equal, stores RCX:RBX there; otherwise it loads the memory into RDX:RAX. With a LOCK prefix it does all this atomically. The operand must be aligned to 16 bytes.

Lock-free data structures use it to update two words at once, such as a pointer and a counter that changes with every update, which defeats the ABA problem of a plain compare-and-exchange. It is the 64-bit counterpart of CMPXCHG8B. Some early x86-64 processors, such as AMD’s K8, lack it, so it has its own CPUID bit, CPUID.01H:ECX[13]; it is part of x86-64-v2.

Instructions

Mnemonics with at least one form in CMPXCHG16B. Each page lists all forms of the mnemonic, including those of other extensions.

Mnemonic	Summary	Forms
CMPXCHG16B	Compares RDX:RAX with 16 aligned bytes of memory: if equal, stores RCX:RBX there and sets ZF, else loads them into RDX:RAX; atomic with LOCK.	2

CPUID and processors

XED splits CMPXCHG16B into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of CMPXCHG16B. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.

ISA set	CPUID	Processors in XED
`CMPXCHG16B` CMPXCHG16B	CMPXCHG16B `CPUID.01H:ECX[13]` CMPXCHG16B	Every x86-64 processor in XED’s model

Instructions

CPUID and processors

Sources