CPUID
ENQCMD
CPUID.(EAX=07H,ECX=0):ECX[29]
Instructions
2 mnemonics
Processors
Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest

Some devices take work through shared work queues: memory-mapped registers to which many programs submit 64-byte commands at once. ENQCMD reads a command from memory, puts the process address space ID (PASID) of the current thread from the IA32_PASID MSR into it, and writes it to the device register with an enqueue store: one 64-byte write that the device either accepts or refuses, which the instruction reports in ZF. A refused command, when the queue is full, is simply retried. ENQCMDS is the privileged form, which takes the PASID and privilege from the command itself.

The PASID tells the device, and the IOMMU, whose address space the command’s addresses belong to, so user programs can hand work to a device directly. The operating system saves IA32_PASID as XSAVE component 10.

Instructions

Mnemonics with at least one form in ENQCMD. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
ENQCMDSends a 64-byte command, tagged with the PASID from the IA32_PASID MSR, to a device's enqueue register and sets ZF if the device did not accept it.1
ENQCMDSKernel version of ENQCMD that takes the PASID and privilege bit of the 64-byte command from its memory operand instead of the IA32_PASID MSR.1

CPUID and processors

XED splits ENQCMD into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of ENQCMD. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
ENQCMD

ENQCMD
CPUID.(EAX=07H,ECX=0):ECX[29] ENQCMD

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.