x86-64.net

Vector (SSE, AVX and AVX10)

F16C

F16C converts packed half-precision values to single precision and back, for data stored in the compact 16-bit format.

CPUID
F16C
CPUID.01H:ECX[29]
Instructions
2 mnemonics
Processors
Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
Linux flag
f16c

Half precision stores a floating-point value in 16 bits, which halves memory and bandwidth for data that does not need more. VCVTPH2PS converts four or eight half-precision values to single precision, and VCVTPS2PH converts back, with a rounding mode from an immediate or MXCSR. F16C does no arithmetic in half precision; AVX512-FP16 and AVX10 do. It is part of x86-64-v3.

Instructions

Mnemonics with at least one form in F16C. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
VCVTPH2PSConverts packed half-precision values to singles, which is exact.4
VCVTPS2PHConverts packed singles to half precision, rounding as an immediate or MXCSR selects.4

CPUID and processors

XED splits F16C into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of F16C. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
F16C

F16C
CPUID.01H:ECX[29] F16C

Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Note: XED gives Bulldozer F16C; GCC enables it from -march=bdver2 (Piledriver) on.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.