x86-64.net

System

FSGSBASE

RDFSBASE, RDGSBASE, WRFSBASE and WRGSBASE read and write the FS and GS segment bases in 64-bit mode, once the operating system has enabled them in CR4.

CPUID
FSGSBASE
CPUID.(EAX=07H,ECX=0):EBX[0]
Instructions
4 mnemonics
Processors
Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

In 64-bit mode the FS and GS segments are mostly just a base address, and FS points to the current thread’s thread-local storage on x86-64 Linux (see the thread pointer). Without these instructions only the kernel could change the bases, so a program asked it with a system call, arch_prctl() on Linux. RDFSBASE, RDGSBASE, WRFSBASE and WRGSBASE read and write them directly.

They work only in 64-bit mode and only after the kernel has set CR4.FSGSBASE, since older kernels relied on the bases they had set; otherwise they raise #UD. Linux reports the enabled state with HWCAP2_FSGSBASE in the auxiliary vector. Intel introduced them with Ivy Bridge.

Instructions

Mnemonics with at least one form in FSGSBASE. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
RDFSBASEReads the FS base, where x86-64 Linux keeps a thread's TLS pointer, into a register; 64-bit mode, when the kernel set CR4.FSGSBASE.1
RDGSBASEReads the GS base into a register; 64-bit mode, when the kernel set CR4.FSGSBASE.1
WRFSBASEWrites the FS base from a register, so a thread can change its TLS pointer without a system call; 64-bit mode, with CR4.FSGSBASE.1
WRGSBASEWrites the GS base from a register; 64-bit mode, when the kernel set CR4.FSGSBASE.1

CPUID and processors

XED splits FSGSBASE into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of FSGSBASE. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
RDWRFSGS

FSGSBASE
CPUID.(EAX=07H,ECX=0):EBX[0] FSGSBASE

Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Linux kernel documentation: Using FS and GS segments in user space applications

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.