x86-64.net

System

FXSR

FXSAVE and FXRSTOR save and restore the x87, MMX and SSE registers and MXCSR in one 512-byte area; the operating system sets CR4.OSFXSR to say it saves SSE state this way.

CPUID
FXSAVE
CPUID.01H:EDX[24]
Instructions
2 mnemonics
Processors
Every x86-64 processor in XED’s model and Zen 3 to Zen 6
Linux flag
fxsr

FXSAVE stores the x87 registers and their control, status and tag words, the MMX registers, the XMM registers and MXCSR in one 512-byte area aligned to 16 bytes, and FXRSTOR loads it back. Unlike the older FSAVE, they cover the SSE state, and the operating system sets CR4.OSFXSR to say that it saves the XMM registers this way, which the processor requires before it runs SSE instructions. Both are part of the x86-64 baseline.

The forms with REX.W, FXSAVE64 and FXRSTOR64, store the x87 instruction and data pointers as 64-bit addresses instead of a segment and a 32-bit offset. The area also became the legacy region of the XSAVE area, which newer operating systems use instead because it covers the AVX and later state too.

Instructions

Mnemonics with at least one form in FXSR. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
FXRSTORRestores the x87, MMX and SSE registers and MXCSR from the 512-byte area that FXSAVE wrote; FXRSTOR64 reads the 64-bit form.2
FXSAVESaves the x87, MMX and SSE registers and MXCSR to a 16-byte aligned 512-byte area; FXSAVE64 stores the x87 pointers as 64-bit values.2

CPUID and processors

XED splits FXSR into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of FXSR. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
FXSAVE

FXSAVE
CPUID.01H:EDX[24] FXSAVE

Every x86-64 processor in XED’s model and Zen 3 to Zen 6
FXSAVE64

FXSAVE + LM
CPUID.01H:EDX[24] FXSAVE
CPUID.80000001H:EDX[29] LM

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.