General-purpose
x86 general-purpose instructions
The integer arithmetic, logic, shift, bit, data-movement, jump and call, string, stack and flag instructions that every x86-64 processor runs, from those of the 8086 to those that 64-bit mode added.
- CPUID
- See the ISA sets below.
- Instructions
- 109 mnemonics
- Processors
- Every x86-64 processor in XED’s model
These are the instructions that every x86-64 program is made of: moves, integer arithmetic and logic, shifts and bit tests, jumps and calls, the stack, the flags and the string instructions. Most go back to the 8086 and the 80386. AMD’s 64-bit mode, which Intel adopted as Intel 64, widened them to 64 bits and dropped a few.
In 64-bit mode
- Operand size. Most instructions default to 32-bit operands; a
REX.W prefix selects 64 bits and 66 selects 16, which the tables
write as
r16/32/64. Writing a 32-bit register clears bits 63 to 32 of the full register, soMOV EAX, ECXzero-extends, while writing an 8- or 16-bit register leaves the rest alone. - Stack and branches. PUSH, POP, CALL, RET and near jumps work on 64-bit values by default, and 32-bit ones cannot be encoded.
- What was dropped. The BCD adjustments (AAA to DAS), BOUND, INTO, PUSHA and POPA, LDS and LES, far jumps and calls to an immediate pointer, and pushes and pops of CS, DS, ES and SS are invalid. Their opcodes found new uses: 40 to 4F, the one-byte INC and DEC, became the REX prefixes, 63 is MOVSXD, C4 and C5 start VEX prefixes, 62 EVEX, and D6 is UDB.
Prefixes
A LOCK prefix makes the memory-destination forms of ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, SBB, SUB, XADD and XOR atomic; XCHG with memory is atomic without it. REP repeats MOVS, STOS, LODS, INS and OUTS RCX times, and REPE and REPNE repeat CMPS and SCAS while the elements are equal or differ. XED lists these prefixed forms as instructions of their own; here they appear on the page of the base mnemonic, as do the size spellings, such as MOVSB to MOVSQ on the MOVS page.
Instructions with a CPUID bit of their own, such as CMOV, POPCNT and BMI1, have their own extension pages, and APX adds registers and forms to many of the instructions here.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| AAA | Corrects AL after adding two unpacked BCD digits: if the low digit exceeds 9 or AF is set, adds 6 to AL and 1 to AH and sets CF and AF; not in 64-bit mode. | 1 |
| AAD | Turns the unpacked BCD digits in AH and AL into the binary number AL plus AH times the immediate base (10 as assembled) before a DIV; not in 64-bit mode. | 1 |
| AAM | Splits AL into two unpacked BCD digits after a MUL: AH gets AL divided by the immediate base (10 as assembled), AL the remainder; not in 64-bit mode. | 1 |
| AAS | Corrects AL after subtracting two unpacked BCD digits: if the low digit exceeds 9 or AF is set, subtracts 6 from AX and 1 from AH; not in 64-bit mode. | 1 |
| ADC | Adds two integers and the carry flag, the step that chains multi-word additions; APX adds a three-operand form. | 24 |
| ADD | Adds two integers and sets the arithmetic flags; APX adds three-operand forms and forms that leave the flags unchanged. | 24 |
| AND | Computes the bitwise AND of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | 24 |
| BOUND | Raises a bound-range exception (#BR) unless a signed array index in a register lies within the two bounds stored in memory; not in 64-bit mode. | 2 |
| BSF | Writes the index of the lowest set bit of the source to the destination; a zero source sets ZF and leaves the destination unchanged. | 2 |
| BSR | Writes the index of the highest set bit of the source to the destination; a zero source sets ZF and leaves the destination unchanged. | 2 |
| BSWAP | Reverses the byte order of a 32- or 64-bit register, converting between little- and big-endian values; with a 16-bit register the result is undefined. | 1 |
| BT | Copies the bit that a register or immediate offset selects in a register or memory operand into CF; a register offset can reach beyond a memory operand. | 4 |
| BTC | Copies the selected bit of a register or memory operand into CF and then inverts it; with LOCK the memory form is atomic. | 6 |
| BTR | Copies the selected bit of a register or memory operand into CF and then clears it; with LOCK the memory form is atomic. | 6 |
| BTS | Copies the selected bit of a register or memory operand into CF and then sets it; with LOCK the memory form is an atomic test-and-set. | 6 |
| CALL | Pushes the return address and jumps to a relative target, one in a register or memory, or a far pointer that also changes the code segment. | 6 |
| CBW | Sign-extends AL into AX, copying bit 7 of AL into every bit of AH (AT&T cbtw). | 1 |
| CDQ | Sign-extends EAX into EDX:EAX, filling EDX with the sign bit of EAX, typically before a 32-bit IDIV (AT&T cltd). | 1 |
| CDQE | Sign-extends EAX into RAX in 64-bit mode; compilers emit it, as cltq in AT&T syntax, to widen a signed 32-bit value. | 1 |
| CLC | Clears the carry flag (CF). | 1 |
| CLD | Clears the direction flag (DF), so that string instructions step upward through memory; the System V and Microsoft ABIs require it clear at calls. | 1 |
| CLI | Clears the interrupt flag (IF) to hold off maskable interrupts; where CPL is above IOPL it faults or clears the virtual interrupt flag instead. | 1 |
| CMC | Inverts the carry flag (CF). | 1 |
| CMP | Compares two operands by subtracting the second from the first, setting the arithmetic flags as SUB would and discarding the result. | 18 |
| CMPS | Compares the element at [RSI] with the one at [RDI], setting the flags as CMP would, and steps both pointers; REPE and REPNE repeat it. | 12 |
| CMPXCHG | Compares the accumulator with the destination: if equal, stores the source there and sets ZF, else loads the destination; atomic with LOCK. | 6 |
| CMPXCHG8B | Compares EDX:EAX with 8 bytes of memory: if equal, stores ECX:EBX there and sets ZF, else loads them into EDX:EAX; atomic with LOCK. | 2 |
| CPUID | Returns identification and feature information about the processor in EAX, EBX, ECX and EDX, for the leaf in EAX and the sub-leaf in ECX. | 1 |
| CQO | Sign-extends RAX into RDX:RAX, filling RDX with the sign bit of RAX, typically before a 64-bit IDIV (AT&T cqto); 64-bit mode only. | 1 |
| CWD | Sign-extends AX into DX:AX, filling DX with the sign bit of AX, typically before a 16-bit IDIV (AT&T cwtd). | 1 |
| CWDE | Sign-extends AX into EAX (AT&T cwtl); in 64-bit mode the write to EAX also clears the upper half of RAX. | 1 |
| DAA | Corrects AL after adding two packed BCD numbers so that it holds two decimal digits, setting CF on a decimal carry; not in 64-bit mode. | 1 |
| DAS | Corrects AL after subtracting two packed BCD numbers so that it holds two decimal digits, setting CF on a decimal borrow; not in 64-bit mode. | 1 |
| DEC | Subtracts one from an operand without changing the carry flag; APX adds three-operand forms and forms that leave the flags unchanged. | 7 |
| DIV | Divides an unsigned double-width dividend in rDX:rAX (AX for bytes) by the operand into quotient and remainder; APX adds a form that keeps the flags. | 4 |
| ENTER | Makes a stack frame: pushes the frame pointer, copies outer frame pointers for nested procedures, and reserves the given bytes of locals. | 1 |
| IDIV | Divides a signed double-width dividend in rDX:rAX (AX for bytes) by the operand into quotient and remainder; APX adds a form that keeps the flags. | 4 |
| IMUL | Multiplies signed integers in one-, two- and three-operand forms; APX adds new-destination, flag-preserving and zero-upper immediate forms. | 10 |
| IN | Reads a byte, word or doubleword from an I/O port, given as an immediate or in DX, into AL, AX or EAX, if IOPL or the TSS permission bitmap allows. | 4 |
| INC | Adds one to an operand without changing the carry flag; APX adds three-operand forms and forms that leave the flags unchanged. | 7 |
| INS | Reads a byte, word or doubleword from the I/O port in DX into memory at [RDI] and steps RDI; REP repeats it RCX times. | 6 |
| INT | Raises the software interrupt whose vector is the immediate, calling its handler through the IDT, as 32-bit Linux system calls do with INT 80h. | 1 |
| INT1 | Raises a debug exception (#DB) with the one-byte opcode F1, meant for hardware debuggers; also known as ICEBP. | 1 |
| INT3 | Raises a breakpoint exception (#BP) with the one-byte opcode CC, which debuggers write over an instruction to set a breakpoint. | 1 |
| INTO | Raises an overflow exception (#OF) if the overflow flag is set; not in 64-bit mode. | 1 |
| IRET | Returns from an interrupt or exception handler, popping the instruction pointer, CS and the flags, and in 64-bit mode RSP and SS too. | 3 |
| Jcc | Jumps to a relative target if a condition on the flags holds, such as JZ when ZF is set or JL when SF differs from OF. | 3 |
| JCXZ | Jumps to a short relative target if CX is zero, without testing or changing the flags; not in 64-bit mode. | 1 |
| JECXZ | Jumps to a short relative target if ECX is zero, without testing or changing the flags. | 1 |
| JMP | Jumps to a relative target, one in a register or memory, or a far pointer that also changes the code segment. | 7 |
| JRCXZ | Jumps to a short relative target if RCX is zero, without testing or changing the flags; 64-bit mode only. | 1 |
| LDS | Loads a far pointer from memory into a register and DS; not in 64-bit mode, where its opcode C5 starts a VEX prefix. | 1 |
| LEA | Computes the address of a memory operand into a register without accessing memory, which compilers also use for arithmetic such as x*5+3. | 1 |
| LEAVE | Releases a stack frame: copies the frame pointer into the stack pointer, then pops the caller's frame pointer. | 1 |
| LES | Loads a far pointer from memory into a register and ES; not in 64-bit mode, where its opcode C4 starts a VEX prefix. | 1 |
| LFS | Loads a far pointer from memory into a register and FS. | 1 |
| LGS | Loads a far pointer from memory into a register and GS. | 1 |
| LODS | Loads the element at [RSI] into AL, AX, EAX or RAX and steps RSI up or down, as the direction flag says. | 8 |
| LOOP | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero. | 1 |
| LOOPE | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero and ZF is set. | 1 |
| LOOPNE | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero and ZF is clear. | 1 |
| LSS | Loads a far pointer from memory into a register and SS, switching the stack segment and pointer with one instruction. | 1 |
| MOV | Copies data between registers, memory and immediates, and moves segment, control and debug registers; those last two only in ring 0. | 30 |
| MOVS | Copies the element at [RSI] to [RDI] and steps both pointers; REP MOVS copies RCX elements, the classic memcpy. | 8 |
| MOVSX | Copies a signed byte or word into a wider register, extending its sign bit. | 7 |
| MOVSXD | Sign-extends a 32-bit register or memory operand into a 64-bit register (AT&T movslq); 64-bit mode only, where it took over ARPL's opcode. | 3 |
| MOVZX | Copies an unsigned byte or word into a wider register, filling the upper bits with zeros. | 7 |
| MUL | Multiplies unsigned integers, producing a double-width result in rDX:rAX (AX for bytes); APX adds a form that leaves the flags unchanged. | 4 |
| NEG | Replaces an operand with its two's complement; APX adds three-operand forms and forms that leave the flags unchanged. | 6 |
| NOP | Does nothing: 90 and the multi-byte 0F 1F forms pad code for alignment, and other opcodes of 0F 18 to 0F 1F are reserved to decode as NOPs. | 28 |
| NOT | Inverts every bit of an operand without changing the flags; APX adds a three-operand form. | 6 |
| OR | Computes the bitwise OR of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | 24 |
| OUT | Writes AL, AX or EAX to an I/O port, given as an immediate or in DX, if IOPL or the TSS permission bitmap allows. | 4 |
| OUTS | Writes a byte, word or doubleword from memory at [RSI] to the I/O port in DX and steps RSI; REP repeats it RCX times. | 6 |
| PAUSE | Tells the processor it is in a spin-wait loop, which avoids a penalty on leaving the loop and saves power; a NOP before the Pentium 4. | 1 |
| POP | Loads the value on top of the stack into a register, memory or a segment register and moves the stack pointer past it. | 8 |
| POPA | Pops the eight general-purpose registers that PUSHA saved, 16-bit or with POPAD 32-bit, discarding the saved stack pointer; not in 64-bit mode. | 2 |
| POPF | Pops the flags from the stack, changing only those the privilege level allows; POPFQ, the 64-bit form, pops RFLAGS. | 3 |
| PUSH | Moves the stack pointer down and stores a register, memory operand, immediate or segment register on top of the stack. | 11 |
| PUSHA | Pushes the eight 16-bit general-purpose registers, or with PUSHAD the 32-bit ones, including the original stack pointer; not in 64-bit mode. | 2 |
| PUSHF | Pushes the flags onto the stack: FLAGS, EFLAGS with PUSHFD, or RFLAGS with PUSHFQ, the default in 64-bit mode. | 3 |
| RCL | Rotates an operand left through the carry flag; APX adds a three-operand form. | 12 |
| RCR | Rotates an operand right through the carry flag; APX adds a three-operand form. | 12 |
| RET | Returns from a procedure: pops the return address (and CS for a far return) and optionally releases stack bytes of the caller's arguments. | 4 |
| ROL | Rotates an operand left; APX adds three-operand forms and forms that leave the flags unchanged. | 12 |
| ROR | Rotates an operand right; APX adds three-operand forms and forms that leave the flags unchanged. | 12 |
| SALC | Sets AL to FFh if the carry flag is set and to 00h if not, like SBB AL, AL but without changing the flags; not in 64-bit mode. | 1 |
| SAR | Shifts an operand right, copying the sign bit into the vacated bits; APX adds three-operand forms and forms that leave the flags unchanged. | 12 |
| SBB | Subtracts an integer and the carry flag, the step that chains multi-word subtractions; APX adds a three-operand form. | 24 |
| SCAS | Compares AL, AX, EAX or RAX with the element at [RDI], setting the flags as CMP would, and steps RDI; REPNE SCAS searches for a value. | 12 |
| SETcc | Writes 1 or 0 to a byte depending on a condition on the flags; APX adds a form that also clears the rest of the destination register. | 2 |
| SHL | Shifts an operand left, filling with zeros (SAL is the same instruction); APX adds three-operand forms and forms that leave the flags unchanged. | 24 |
| SHLD | Shifts an operand left and fills the vacated bits from a second register; APX adds three-operand forms and forms that leave the flags unchanged. | 4 |
| SHR | Shifts an operand right, filling with zeros; APX adds three-operand forms and forms that leave the flags unchanged. | 12 |
| SHRD | Shifts an operand right and fills the vacated bits from a second register; APX adds three-operand forms and forms that leave the flags unchanged. | 4 |
| STC | Sets the carry flag (CF). | 1 |
| STD | Sets the direction flag (DF), so that string instructions step downward through memory. | 1 |
| STI | Sets the interrupt flag (IF), accepting maskable interrupts after the next instruction; where CPL is above IOPL it faults or sets the virtual one instead. | 1 |
| STOS | Stores AL, AX, EAX or RAX at [RDI] and steps RDI; REP STOS fills RCX elements, the classic memset. | 8 |
| SUB | Subtracts one integer from another and sets the arithmetic flags; APX adds three-operand forms and forms that leave the flags unchanged. | 24 |
| TEST | ANDs two operands to set SF, ZF and PF and clear CF and OF, discarding the result; TEST with the same register twice checks it for zero. | 14 |
| UD0 | Raises an invalid-opcode exception (#UD); some processors decode it without the ModR/M byte and operands that others read. | 3 |
| UD1 | Raises an invalid-opcode exception (#UD); its register and memory operands are decoded but not used. | 2 |
| UD2 | Raises an invalid-opcode exception (#UD); compilers emit it for __builtin_trap and code that must not be reached. | 1 |
| UDB | Raises an invalid-opcode exception (#UD) with the one-byte opcode D6, in 64-bit mode, where SALC is not available. | 1 |
| XADD | Exchanges a register with the destination and stores their sum in the destination; with LOCK it is the atomic fetch-and-add. | 6 |
| XCHG | Swaps two operands; with a memory operand it is atomic even without a LOCK prefix. | 5 |
| XLAT | Replaces AL with the byte at RBX plus AL, a table lookup; XLATB is the spelling without operands. | 1 |
| XOR | Computes the bitwise exclusive OR of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | 24 |
CPUID and processors
XED splits General-purpose into 12 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors in XED |
|---|---|---|
FAT_NOP | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
I186 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
I386 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
I486REAL | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
I86 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
LONGMODE | LM | Every x86-64 processor in XED’s model |
PAUSE | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
PENTIUMREAL | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
PPRO | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
PPRO_UD0_LONG | No CPUID bit: part of the base instruction set. | NetBurst (Prescott, Nocona), Core (Merom, Conroe), Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2 |
PPRO_UD0_SHORT | No CPUID bit: part of the base instruction set. | Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Granite Rapids, Diamond Rapids, Bonnell, Saltwell, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Sierra Forest, Clearwater Forest |
PREFETCH_NOP | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.