x86-64.net

Cryptography

GFNI

Galois field instructions: byte multiplication in GF(2^8) and affine transformations of bytes by an 8x8 bit matrix, in legacy and VEX forms.

CPUID
GFNI
CPUID.(EAX=07H,ECX=0):ECX[8]
Instructions
6 mnemonics
Processors
Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen 4, Zen 5, Zen 6
Linux flag
gfni

Galois field instructions work on bytes as elements of GF(2^8). GF2P8MULB multiplies them modulo the polynomial of AES. GF2P8AFFINEQB multiplies each byte, as a vector of bits, by an 8x8 bit matrix and adds a constant, and GF2P8AFFINEINVQB first replaces each byte with its inverse, which together give the AES S-box. An affine transform with a suitable matrix can also reverse or move the bits of each byte. The legacy forms are on these pages, the VEX and EVEX forms on those of VGF2P8MULB and its relatives.

Instructions

Mnemonics with at least one form in GFNI. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
GF2P8AFFINEINVQBInverts each byte in GF(2^8), then applies an affine transformation given by an 8x8 bit matrix and an immediate constant.2
GF2P8AFFINEQBApplies an affine transformation to each byte, given by an 8x8 bit matrix from the source and an immediate constant.2
GF2P8MULBMultiplies bytes in the finite field GF(2^8) defined by the AES polynomial x^8 + x^4 + x^3 + x + 1.2
VGF2P8AFFINEINVQBReplaces each byte with its inverse in GF(2^8), then applies an affine transformation given by an 8x8 bit matrix and an immediate constant.4
VGF2P8AFFINEQBApplies an affine transformation to each byte, given by an 8x8 bit matrix from the second source and an immediate constant.4
VGF2P8MULBMultiplies bytes in the finite field GF(2^8) defined by the AES polynomial x^8 + x^4 + x^3 + x + 1.4

CPUID and processors

XED splits GFNI into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of GFNI. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX_GFNI

GFNI + AVX
CPUID.(EAX=07H,ECX=0):ECX[8] GFNI
CPUID.01H:ECX[28] AVX

Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Zen 4, Zen 5, Zen 6
GFNI

GFNI
CPUID.(EAX=07H,ECX=0):ECX[8] GFNI

Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.