CPUID
HRESET
CPUID.(EAX=07H,ECX=1):EAX[22]
Instructions
1 mnemonic
Processors
Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest

Processors keep history about the code they run, for example to predict how a thread will behave. HRESET lets the operating system reset selected parts of that history, for example on a context switch, so that what one thread did does not influence the treatment of the next. CPUID leaf 20H lists which components can be reset, the operating system enables them in the IA32_HRESET_ENABLE MSR, and EAX selects which to reset; the immediate operand is ignored. HRESET runs only at privilege level 0.

Instructions

Mnemonics with at least one form in HRESET. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
HRESETResets the parts of the processor's prediction history that EAX selects and the operating system enabled in IA32_HRESET_ENABLE; allowed only in ring 0.1

CPUID and processors

XED splits HRESET into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of HRESET. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
HRESET

HRESET
CPUID.(EAX=07H,ECX=1):EAX[22] HRESET

Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.