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System

INVLPGB and TLBSYNC (AMD)

INVLPGB invalidates TLB entries on every processor of a system at once, without interrupts between processors, and TLBSYNC waits for them to finish.

An AMD extension: Intel processors do not have this instruction.

CPUID
INVLPGB
CPUID.80000008H:EBX[3]
Instructions
2 mnemonics
Processors
Zen 3, Zen 4, Zen 5, Zen 6

Note: Only the EPYC server processors have INVLPGB and TLBSYNC: AMD's references for the Ryzen processors of Zen 3, Zen 4 and Zen 5 leave CPUID_Fn80000008_EBX[INVLPGB] (bit 3) clear. Zen 6 is listed because Zen 5 has them, until AMD publishes a Processor Programming Reference for Zen 6.

Instructions

Mnemonics with at least one form in INVLPGB. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
INVLPGBInvalidates TLB entries that a descriptor in rAX and EDX selects on every processor of the system, not just this one.1
TLBSYNCWaits until every processor has carried out the INVLPGB invalidations that this processor sent.1

CPUID and processors

XED splits INVLPGB into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of INVLPGB. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AMD_INVLPGB

INVLPGB
CPUID.80000008H:EBX[3] INVLPGB

Zen 3, Zen 4, Zen 5, Zen 6

Note: Only the EPYC server processors have INVLPGB and TLBSYNC: AMD's references for the Ryzen processors of Zen 3, Zen 4 and Zen 5 leave CPUID_Fn80000008_EBX[INVLPGB] (bit 3) clear. Zen 6 is listed because Zen 5 has them, until AMD publishes a Processor Programming Reference for Zen 6.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.36, March 2024), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.