x86-64.net

System

INVPCID

INVPCID invalidates TLB entries by process-context identifier (PCID): of one address, of one context, or of all contexts with or without global pages; ring 0 only.

CPUID
INVPCID
CPUID.(EAX=07H,ECX=0):EBX[10]
Instructions
1 mnemonic
Processors
Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Zen 3, Zen 4, Zen 5, Zen 6

With CR4.PCIDE set, each TLB entry is tagged with the 12-bit process-context identifier (PCID) that was in CR3 when it was made, so the processor can keep the translations of several address spaces across a switch of CR3. INVPCID then invalidates entries selectively, by a type in a register and a descriptor in memory: those of one address in one context, all of one context, or those of all contexts with or without global pages. It runs only at privilege level 0; APX adds an EVEX form.

Instructions

Mnemonics with at least one form in INVPCID. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
INVPCIDInvalidates TLB entries and paging-structure caches for one address, one process-context identifier or all of them, as the type in a register selects.2

CPUID and processors

XED splits INVPCID into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of INVPCID. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
INVPCID

INVPCID
CPUID.(EAX=07H,ECX=0):EBX[10] INVPCID

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.