CPUID
LAHF
CPUID.80000001H:ECX[0]
Instructions
2 mnemonics
Processors
Every x86-64 processor in XED’s model
Linux flag
lahf_lm

LAHF copies the arithmetic flags SF, ZF, AF, PF and CF into AH, and SAHF writes them back, a cheaper way to save and restore them than PUSHF and POPF, which emulators and compilers use.

The first x86-64 processors, AMD’s early K8 revisions and Intel’s NetBurst models with Intel 64, did not support them in 64-bit mode. CPUID.80000001H:ECX[0] (Linux flag lahf_lm) says whether they work there; in the other modes they always do. The bit is part of x86-64-v2.

Instructions

Mnemonics with at least one form in LAHF-SAHF. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
LAHFCopies SF, ZF, AF, PF and CF into bits 7, 6, 4, 2 and 0 of AH; 64-bit mode needs the LAHF-SAHF feature.1
SAHFStores bits 7, 6, 4, 2 and 0 of AH into SF, ZF, AF, PF and CF; 64-bit mode needs the LAHF-SAHF feature.1

CPUID and processors

XED splits LAHF-SAHF into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of LAHF-SAHF. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
LAHF

LAHF
CPUID.80000001H:ECX[0] LAHF

Every x86-64 processor in XED’s model

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.