System
LKGS
Loads the GS segment from a selector but writes the descriptor's base address to the IA32_KERNEL_GS_BASE MSR, so a FRED kernel can change a thread's GS without losing its own GS base.
- CPUID
- LKGS
CPUID.(EAX=07H,ECX=1):EAX[18] - Instructions
- 1 mnemonic
- Processors
- Panther Lake, Nova Lake, Diamond Rapids
64-bit kernels keep two GS base addresses: the user’s, in the GS segment itself, and the kernel’s, in the IA32_KERNEL_GS_BASE MSR, and switch them with SWAPGS. Loading a new user GS selector from inside the kernel is awkward, because MOV to GS overwrites the base the kernel is currently using. LKGS does the same load but puts the base into IA32_KERNEL_GS_BASE, where the user value waits until the return to user mode swaps it back in.
LKGS belongs to the FRED architecture, where SWAPGS no longer exists, but it has its own CPUID bit, CPUID.(EAX=07H,ECX=1):EAX[18], because kernels without FRED can use it too. It works only in 64-bit mode at privilege level 0.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| LKGS | Loads GS from a selector but puts the descriptor's base in the IA32_KERNEL_GS_BASE MSR instead of the GS base; ring 0 of 64-bit mode only. | 2 |
CPUID and processors
XED splits LKGS into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors in XED |
|---|---|---|
LKGS | LKGS | Panther Lake, Nova Lake, Diamond Rapids |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Flexible Return and Event Delivery (FRED) Specification (346446-009)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.