x86-64.net

System

LKGS

Loads the GS segment from a selector but writes the descriptor's base address to the IA32_KERNEL_GS_BASE MSR, so a FRED kernel can change a thread's GS without losing its own GS base.

CPUID
LKGS
CPUID.(EAX=07H,ECX=1):EAX[18]
Instructions
1 mnemonic
Processors
Panther Lake, Nova Lake, Diamond Rapids, Zen 6

64-bit kernels keep two GS base addresses: the user’s, in the GS segment itself, and the kernel’s, in the IA32_KERNEL_GS_BASE MSR, and switch them with SWAPGS. Loading a new user GS selector from inside the kernel is awkward, because MOV to GS overwrites the base the kernel is currently using. LKGS does the same load but puts the base into IA32_KERNEL_GS_BASE, where the user value waits until the return to user mode swaps it back in.

LKGS belongs to the FRED architecture, where SWAPGS no longer exists, but it has its own CPUID bit, CPUID.(EAX=07H,ECX=1):EAX[18], because kernels without FRED can use it too. It works only in 64-bit mode at privilege level 0.

Instructions

Mnemonics with at least one form in LKGS. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
LKGSLoads GS from a selector but puts the descriptor's base in the IA32_KERNEL_GS_BASE MSR instead of the GS base; ring 0 of 64-bit mode only.2

CPUID and processors

XED splits LKGS into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of LKGS. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
LKGS

LKGS
CPUID.(EAX=07H,ECX=1):EAX[18] LKGS

Panther Lake, Nova Lake, Diamond Rapids, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Flexible Return and Event Delivery (FRED) Specification (346446-009)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.