x86-64.net

General-purpose

LZCNT

LZCNT counts the leading zero bits of an operand; unlike BSR it has a defined result for zero, the operand size, and it reports that case in CF.

CPUID
LZCNT
CPUID.80000001H:ECX[5]
Instructions
1 mnemonic
Processors
Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2
Linux flag
abm

LZCNT counts the zero bits above the highest set bit. For a zero operand it returns the operand size (32 for a 32-bit operand) and sets CF, where BSR leaves its destination unchanged and only sets ZF, so code no longer needs a separate test for zero.

Its encoding is BSR with an F3 prefix, which older processors ignore: there the same bytes run BSR and return the index of the highest set bit instead of the count, a different number for any operand. Check CPUID.80000001H:ECX[5] before using it. AMD introduced LZCNT with K10 as part of its Advanced Bit Manipulation, Intel with Haswell, and it is part of x86-64-v3.

Instructions

Mnemonics with at least one form in LZCNT. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
LZCNTCounts the leading zero bits of an operand; APX adds a form that leaves the flags unchanged.2

CPUID and processors

XED splits LZCNT into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of LZCNT. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
LZCNT

LZCNT
CPUID.80000001H:ECX[5] LZCNT

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.