Memory, caches and atomics
MCOMMIT
MCOMMIT waits until earlier stores to memory with delayed error reporting have completed and says in CF whether any of them failed.
An AMD extension: Intel processors do not have this instruction.
- CPUID
- MCOMMIT
CPUID.80000008H:EBX[8] - Instructions
- 1 mnemonic
- Processors
- Zen 2, Zen 3
Note: Only the EPYC 7002 (Zen 2) and EPYC 7003 (Zen 3) server processors have MCOMMIT. AMD's references for the Ryzen processors of Zen 2 and Zen 3 leave CPUID_Fn80000008_EBX[MCOMMIT] (bit 8) clear, and so do its references for Zen 4 and Zen 5, EPYC included.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| MCOMMIT | Waits until earlier stores to memory with delayed error reporting have completed, and clears CF if any of them failed. | 1 |
CPUID and processors
XED splits MCOMMIT into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors |
|---|---|---|
MCOMMIT | MCOMMIT | Zen 2, Zen 3 Note: Only the EPYC 7002 (Zen 2) and EPYC 7003 (Zen 3) server processors have MCOMMIT. AMD's references for the Ryzen processors of Zen 2 and Zen 3 leave CPUID_Fn80000008_EBX[MCOMMIT] (bit 8) clear, and so do its references for Zen 4 and Zen 5, EPYC included. |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.38, July 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.