MMX instruction set extension

MMX, introduced with the Pentium MMX in 1997, was the first SIMD extension of x86: eight 64-bit registers, MM0 to MM7, with integer instructions on packed bytes, words and doublewords, with or without saturation. The MMX registers are the significands of the x87 data registers, so the two cannot be used at once: an MMX instruction marks the x87 stack as in use, and code has to run EMMS before any x87 instruction follows.

SSE2 brought the same operations to the 128-bit XMM registers, where the pages of these mnemonics list them next to the MMX forms, and 64-bit compilers do not emit MMX code for ordinary C. The MMX forms remain in old libraries and in 32-bit code. SSE and SSE2 added a few more instructions for MMX registers, such as PSHUFW and PADDQ; they need the CPUID bit of the extension that added them and are listed there.

Instructions

Mnemonics with at least one form in MMX. Each page lists all forms of the mnemonic, including those of other extensions.

Mnemonic	Summary	Forms
EMMS	Marks every x87 register empty at the end of MMX code, so that x87 instructions can use the register stack again.	1
MOVD	Moves 32 bits between an MMX or XMM register and a general-purpose register or memory, zeroing the rest of a vector register.	4
MOVQ	Moves 64 bits between MMX or XMM registers, general-purpose registers and memory, zeroing the rest of an XMM destination.	8
PACKSSDW	Narrows signed doublewords of two MMX or XMM operands to words with signed saturation.	2
PACKSSWB	Narrows signed words of two MMX or XMM operands to bytes with signed saturation.	2
PACKUSWB	Narrows signed words of two MMX or XMM operands to bytes with unsigned saturation.	2
PADDB	Adds packed bytes of MMX or XMM registers, wrapping around on overflow.	2
PADDD	Adds packed doublewords of MMX or XMM registers, wrapping around on overflow.	2
PADDSB	Adds packed signed bytes of MMX or XMM registers with signed saturation.	2
PADDSW	Adds packed signed words of MMX or XMM registers with signed saturation.	2
PADDUSB	Adds packed unsigned bytes of MMX or XMM registers with unsigned saturation.	2
PADDUSW	Adds packed unsigned words of MMX or XMM registers with unsigned saturation.	2
PADDW	Adds packed words of MMX or XMM registers, wrapping around on overflow.	2
PAND	Computes the bitwise AND of two MMX or XMM operands.	2
PANDN	Computes the bitwise AND of the inverted destination with the source, in MMX or XMM registers.	2
PCMPEQB	Compares packed bytes of MMX or XMM registers for equality, into all-ones or all-zeros bytes.	2
PCMPEQD	Compares packed doublewords of MMX or XMM registers for equality, into all-ones or all-zeros elements.	2
PCMPEQW	Compares packed words of MMX or XMM registers for equality, into all-ones or all-zeros words.	2
PCMPGTB	Tests packed signed bytes of MMX or XMM registers for greater than, into all-ones or all-zeros bytes.	2
PCMPGTD	Tests packed signed doublewords of MMX or XMM registers for greater than, into all-ones or all-zeros elements.	2
PCMPGTW	Tests packed signed words of MMX or XMM registers for greater than, into all-ones or all-zeros words.	2
PMADDWD	Multiplies packed signed words of MMX or XMM registers and adds adjacent products into doublewords.	2
PMULHW	Multiplies packed signed words of MMX or XMM registers and keeps the high 16 bits of each product.	2
PMULLW	Multiplies packed words of MMX or XMM registers and keeps the low 16 bits of each product.	2
POR	Computes the bitwise OR of two MMX or XMM operands.	2
PSLLD	Shifts packed doublewords of an MMX or XMM register left by a count from a register, memory or an immediate.	3
PSLLQ	Shifts packed quadwords of an MMX or XMM register left by a count from a register, memory or an immediate.	3
PSLLW	Shifts packed words of an MMX or XMM register left by a count from a register, memory or an immediate.	3
PSRAD	Shifts packed doublewords of an MMX or XMM register right arithmetically by a count from a register, memory or an immediate.	3
PSRAW	Shifts packed words of an MMX or XMM register right arithmetically by a count from a register, memory or an immediate.	3
PSRLD	Shifts packed doublewords of an MMX or XMM register right logically by a count from a register, memory or an immediate.	3
PSRLQ	Shifts packed quadwords of an MMX or XMM register right logically by a count from a register, memory or an immediate.	3
PSRLW	Shifts packed words of an MMX or XMM register right logically by a count from a register, memory or an immediate.	3
PSUBB	Subtracts packed bytes of MMX or XMM registers, wrapping around on overflow.	2
PSUBD	Subtracts packed doublewords of MMX or XMM registers, wrapping around on overflow.	2
PSUBSB	Subtracts packed signed bytes of MMX or XMM registers with signed saturation.	2
PSUBSW	Subtracts packed signed words of MMX or XMM registers with signed saturation.	2
PSUBUSB	Subtracts packed unsigned bytes of MMX or XMM registers with unsigned saturation.	2
PSUBUSW	Subtracts packed unsigned words of MMX or XMM registers with unsigned saturation.	2
PSUBW	Subtracts packed words of MMX or XMM registers, wrapping around on overflow.	2
PUNPCKHBW	Interleaves the high bytes of two MMX or XMM operands.	2
PUNPCKHDQ	Interleaves the high doublewords of two MMX or XMM operands.	2
PUNPCKHWD	Interleaves the high words of two MMX or XMM operands.	2
PUNPCKLBW	Interleaves the low bytes of two MMX or XMM operands.	2
PUNPCKLDQ	Interleaves the low doublewords of two MMX or XMM operands.	2
PUNPCKLWD	Interleaves the low words of two MMX or XMM operands.	2
PXOR	Computes the bitwise XOR of two MMX or XMM operands; with the same register twice it zeroes it.	2

CPUID and processors

XED splits MMX into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of MMX. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

Instructions

CPUID and processors

Sources