x86-64.net

System

MONITOR/MWAIT

MONITOR arms address monitoring and MWAIT waits in an optimized state for a store to the monitored range or an interrupt; kernels use them to idle processors.

CPUID
MONITOR
CPUID.01H:ECX[3]
Instructions
2 mnemonics
Processors
Every x86-64 processor in XED’s model and Zen 3 to Zen 6

MONITOR arms the processor’s address monitor on the range that holds the address in RAX, and MWAIT then waits until something writes to that range, an interrupt arrives or another break event occurs. While it waits the core can enter an optimized state, a C-state that EAX hints at, which is how operating systems idle a processor and how one CPU can wake another by writing to a shared flag instead of sending an interrupt.

Both run only at privilege level 0. CPUID leaf 05H gives the size of the monitored range and the supported states. WAITPKG provides similar waits for user code.

Instructions

Mnemonics with at least one form in MONITOR/MWAIT. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
MONITORArms the address monitor on the range holding the address in RAX, so that a later MWAIT waits for a store to it; ring 0 only.1
MWAITWaits in an optimized state that EAX hints at until the monitored range is written or an interrupt arrives; ring 0 only.1

CPUID and processors

XED splits MONITOR/MWAIT into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of MONITOR/MWAIT. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
MONITOR

MONITOR
CPUID.01H:ECX[3] MONITOR

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.