x86-64.net

Memory, caches and atomics

MOVDIR64B

MOVDIR64B copies 64 bytes from memory to a 64-byte aligned address as one direct store, the way to hand a work descriptor to a device.

CPUID
MOVDIR64B
CPUID.(EAX=07H,ECX=0):ECX[28]
Instructions
1 mnemonic
Processors
Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Snow Ridge, Sierra Forest, Clearwater Forest, Zen 5, Zen 6
Linux flag
movdir64b

MOVDIR64B reads 64 bytes from memory and writes them to a 64-byte aligned destination, whose address is in a register, as one direct store: the device receives all 64 bytes in one write, not combined with younger stores and not through the caches. The read need not be atomic. Drivers use it to hand a work descriptor to a device queue that one program owns; for queues that many programs share there is ENQCMD, which also reports whether the device took the command.

Instructions

Mnemonics with at least one form in MOVDIR64B. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
MOVDIR64BCopies 64 bytes from memory to a 64-byte-aligned destination as one direct store that is written atomically and bypasses the caches.1

CPUID and processors

XED splits MOVDIR64B into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of MOVDIR64B. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
MOVDIR64B

MOVDIR64B
CPUID.(EAX=07H,ECX=0):ECX[28] MOVDIR64B

Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Snow Ridge, Sierra Forest, Clearwater Forest, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.