x86-64.net

Memory, caches and atomics

MOVDIRI

MOVDIRI writes a doubleword or quadword to memory with a direct store that bypasses the caches, for writing to device registers.

CPUID
MOVDIRI
CPUID.(EAX=07H,ECX=0):ECX[27]
Instructions
1 mnemonic
Processors
Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Snow Ridge, Sierra Forest, Clearwater Forest, Zen 5, Zen 6
Linux flag
movdiri

MOVDIRI writes a doubleword or quadword from a register to memory with a direct store: it uses the write-combining protocol whatever the memory type, so the data does not enter the caches, and the store is not combined with younger stores to the same address. An aligned direct store reaches its destination in one write, which suits device registers such as doorbells. Direct stores are weakly ordered, so software adds a fence where it needs order. MOVDIR64B does the same for 64 bytes.

Instructions

Mnemonics with at least one form in MOVDIRI. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
MOVDIRIStores a 32- or 64-bit register to memory as a direct store that bypasses the caches.2

CPUID and processors

XED splits MOVDIRI into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of MOVDIRI. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
MOVDIRI

MOVDIRI
CPUID.(EAX=07H,ECX=0):ECX[27] MOVDIRI

Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Snow Ridge, Sierra Forest, Clearwater Forest, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.