Memory, caches and atomics
MOVRS
Loads and a prefetch with a read-shared hint, for data that many cores read but rarely write.
- CPUID
- MOVRS
CPUID.(EAX=07H,ECX=1):EAX[31] - Instructions
- 6 mnemonics
- Processors
- Nova Lake, Diamond Rapids
MOVRS adds loads with a read-shared hint: the data is likely to be read by other processors before anyone writes it, so the processor may keep it in shared cache levels. MOVRS loads a general-purpose register, the VMOVRS instructions such as VMOVRSD load a vector register (these need AVX10 as well), and PREFETCHRST2 prefetches with the same hint. The hint never changes results; a later write to such data only performs worse than it would have after an ordinary load. AMX-MOVRS adds the same hint to tile loads.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| MOVRS | Loads a register from memory with a hint that other cores are likely to read the same data before it is written. | 2 |
| PREFETCHRST2 | Prefetches data with a hint that several cores are likely to read it before it is written, into caches chosen for read sharing. | 1 |
| VMOVRSB | Loads a vector of bytes under a write mask, with a hint that other cores are likely to read the same data before it is written. | 3 |
| VMOVRSD | Loads a vector of doublewords under a write mask, with a hint that other cores are likely to read the same data before it is written. | 3 |
| VMOVRSQ | Loads a vector of quadwords under a write mask, with a hint that other cores are likely to read the same data before it is written. | 3 |
| VMOVRSW | Loads a vector of words under a write mask, with a hint that other cores are likely to read the same data before it is written. | 3 |
CPUID and processors
XED splits MOVRS into 4 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX10_MOVRS_128 | MOVRS + AVX10 | Nova Lake, Diamond Rapids |
AVX10_MOVRS_256 | MOVRS + AVX10 | Nova Lake, Diamond Rapids |
AVX10_MOVRS_512 | MOVRS + AVX10 | Nova Lake, Diamond Rapids |
MOVRS | MOVRS | Nova Lake, Diamond Rapids |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
- Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.