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System

MSR_IMM

Forms of RDMSR and WRMSRNS that take the register number as an immediate and the value in any general-purpose register.

CPUID
MSR_IMM
CPUID.(EAX=07H,ECX=1):ECX[5]
Instructions
2 mnemonics
Processors
Clearwater Forest

MSR_IMM adds forms of RDMSR and WRMSRNS that take the MSR address as a 32-bit immediate and the value in any 64-bit general-purpose register, instead of ECX and EDX:EAX, which saves loading ECX and splitting the value across two registers when the address is a constant. The forms exist only in 64-bit mode; Intel lists Clearwater Forest as the first processor with them.

Instructions

Mnemonics with at least one form in MSR_IMM. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
RDMSRReads a model-specific register into EDX:EAX, or with MSR_IMM into any 64-bit register from an MSR number given as an immediate; allowed only in ring 0.1
WRMSRNSWrites a model-specific register like WRMSR but without serializing the processor; the MSR_IMM form takes the MSR number as an immediate.1

CPUID and processors

XED splits MSR_IMM into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of MSR_IMM. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
MSR_IMM

MSR_IMM
CPUID.(EAX=07H,ECX=1):ECX[5] MSR_IMM

Clearwater Forest

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.