System
MSRLIST
Reads or writes a list of up to 64 model-specific registers with one instruction.
- CPUID
- MSRLIST
CPUID.(EAX=07H,ECX=1):EAX[27] - Instructions
- 2 mnemonics
- Processors
- Panther Lake, Nova Lake, Diamond Rapids, Sierra Forest, Clearwater Forest
Operating systems read and write many model-specific registers on every context switch or VM transition. RDMSRLIST and WRMSRLIST handle up to 64 of them in one instruction: RSI points to a table of MSR addresses, RDI to a table of values, and each set bit in RCX selects one table entry. The instruction clears each bit as it finishes that entry, so, like a REP string instruction, it can be interrupted and resumed. RDMSRLIST may read the MSRs out of order unless the table includes the IA32_BARRIER MSR; WRMSRLIST writes them in order and, like WRMSRNS, does not serialize. Both run only in 64-bit mode at privilege level 0.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| RDMSRLIST | Reads up to 64 model-specific registers whose addresses are listed in a table in memory, selected by a bit mask in RCX, into a second table. | 1 |
| WRMSRLIST | Writes up to 64 model-specific registers from a table in memory to the addresses listed in a second table, selected by a bit mask in RCX. | 1 |
CPUID and processors
XED splits MSRLIST into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors in XED |
|---|---|---|
MSRLIST | MSRLIST | Panther Lake, Nova Lake, Diamond Rapids, Sierra Forest, Clearwater Forest |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.