x86-64.net

Cryptography

PCLMULQDQ

PCLMULQDQ multiplies two 64-bit polynomials over GF(2), without carries, into a 128-bit product.

CPUID
PCLMULQDQ
CPUID.01H:ECX[1]
Instructions
1 mnemonic
Processors
Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
Linux flag
pclmulqdq

PCLMULQDQ multiplies two 64-bit operands as polynomials over GF(2): partial products are combined with XOR instead of addition, so there are no carries, and the result has 127 bits. An immediate chooses which quadword of each operand to use. Arithmetic in binary fields, as in the GHASH of AES-GCM and in CRC computations, is built from such multiplications. VPCLMULQDQ has the VEX and EVEX forms.

Instructions

Mnemonics with at least one form in PCLMULQDQ. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
PCLMULQDQCarry-less multiplies one quadword of each operand, chosen by an immediate, into a 128-bit product.2

CPUID and processors

XED splits PCLMULQDQ into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of PCLMULQDQ. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
PCLMULQDQ

PCLMULQDQ
CPUID.01H:ECX[1] PCLMULQDQ

Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.