x86-64.net

General-purpose

POPCNT

POPCNT counts the set bits of a 16-, 32- or 64-bit operand in one instruction.

CPUID
POPCNT
CPUID.01H:ECX[23]
Instructions
1 mnemonic
Processors
Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2
Linux flag
popcnt

POPCNT returns the number of set bits of a 16-, 32- or 64-bit register or memory operand, sets ZF if the operand was zero and clears the other arithmetic flags. Without it, counting bits takes a sequence of shifts, masks and additions. AMD introduced it with K10, Intel with Nehalem, and it is part of x86-64-v2, so code built for that level uses it for __builtin_popcount and std::popcount.

It has its own CPUID bit, CPUID.01H:ECX[23], although XED files it with SSE4. APX adds a form that leaves the flags unchanged.

Instructions

Mnemonics with at least one form in POPCNT. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
POPCNTCounts the bits that are set in an operand; APX adds a form that leaves the flags unchanged.2

CPUID and processors

XED splits POPCNT into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of POPCNT. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
POPCNT

POPCNT
CPUID.01H:ECX[23] POPCNT

Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.