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Memory, caches and atomics

PREFETCHI

Prefetches code rather than data, from a RIP-relative address, into the cache hierarchy.

CPUID
PREFETCHI
CPUID.(EAX=07H,ECX=1):EDX[14]
Instructions
2 mnemonics
Processors
Granite Rapids, Diamond Rapids, Clearwater Forest, Zen 5, Zen 6

Note: Zen 5 and Zen 6 report PREFETCHIT0 and PREFETCHIT1 in CPUID_Fn80000021_EAX[PREFETCHI] (bit 20), a bit of AMD's own, and leave Intel's bit, CPUID.(EAX=07H,ECX=1):EDX[14], clear.

PREFETCHIT0 and PREFETCHIT1 prefetch code rather than data: PREFETCHIT0 into all cache levels, PREFETCHIT1 into all but the first. They work only with a RIP-relative address in 64-bit mode and are NOPs otherwise, and the address should be the start of a real instruction, typically code that is about to run. Like all prefetches they are only hints.

Intel lists Granite Rapids, Clearwater Forest and Nova Lake as the first processors with PREFETCHI; XED’s chip model has Granite Rapids, Clearwater Forest and Diamond Rapids, but not Nova Lake. Among AMD’s processors, GCC’s -march=znver5 enables PREFETCHI for Zen 5, which reports it in a CPUID bit of AMD’s own rather than Intel’s, as the note under the list says. AMD’s first references for Zen 6, 58264 and 58655, set the same bit.

Instructions

Mnemonics with at least one form in PREFETCHI. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
PREFETCHIT0Prefetches code at a RIP-relative address into all cache levels; a no-op without RIP-relative addressing or on older processors.1
PREFETCHIT1Prefetches code at a RIP-relative address into every cache level but L1; a no-op without RIP-relative addressing or on older processors.1

CPUID and processors

XED splits PREFETCHI into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of PREFETCHI. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
ICACHE_PREFETCH

PREFETCHI
CPUID.(EAX=07H,ECX=1):EDX[14] PREFETCHI

Granite Rapids, Diamond Rapids, Clearwater Forest, Zen 5, Zen 6

Note: XED's Nova Lake lacks PREFETCHIT0 and PREFETCHIT1, which GCC's -march=novalake enables and Intel's extensions reference lists for Nova Lake.

Note: Zen 5 and Zen 6 report PREFETCHIT0 and PREFETCHIT1 in CPUID_Fn80000021_EAX[PREFETCHI] (bit 20), a bit of AMD's own, and leave Intel's bit, CPUID.(EAX=07H,ECX=1):EDX[14], clear.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
  5. GCC 14 release notes (x86 target)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.