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Memory, caches and atomics

PREFETCH and PREFETCHW

PREFETCH and PREFETCHW, which came with 3DNow!, fetch a cache line ahead of a read or a write; every AMD64 processor has them, and Intel's processors have PREFETCHW.

CPUID
3DNowPrefetch
CPUID.80000001H:ECX[8]
Instructions
3 mnemonics
Processors
Every x86-64 processor in XED’s model and Zen 3 to Zen 6

AMD introduced PREFETCH and PREFETCHW with 3DNow!. Both fetch the cache line that holds an address; PREFETCHW asks for it in a state that lets the processor write it, so that a following store does not have to wait for other caches to give the line up. AMD’s manual says that every processor with long mode (64-bit mode) or 3DNow! supports them, and that the reserved forms of the opcode, 0F 0D /2 to /7, act as PREFETCH; the dedicated CPUID bit is 3DNowPrefetch. Intel’s manual documents PREFETCHW (0F 0D /1) as well, and XED decodes 0F 0D /2 as the Xeon Phi’s PREFETCHWT1 and 0F 0D /3 as another PREFETCHW.

Instructions

Mnemonics with at least one form in PREFETCHW. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
NOPDoes nothing: 90 and the multi-byte 0F 1F forms pad code for alignment, and other opcodes of 0F 18 to 0F 1F are reserved to decode as NOPs.1
PREFETCHLoads the cache line of a byte in memory into the first-level data cache ahead of use; AMD lets reserved 0F 0D forms act the same.5
PREFETCHWLoads the cache line of a byte in memory into the cache ahead of a write, in the modified state on AMD processors.2

CPUID and processors

XED splits PREFETCHW into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of PREFETCHW. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
PREFETCH_NOP

3DNowPrefetch
CPUID.80000001H:ECX[8] 3DNowPrefetch

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.36, March 2024), Wayback Machine copy of AMD's PDF
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.