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Memory, caches and atomics

PREFETCHWT1

PREFETCHWT1 prefetches a cache line into the second-level cache in the exclusive state, ready for the processor to write it.

Only the Xeon Phi processors Knights Landing and Knights Mill have this instruction; no other Intel processor supports it.

CPUID
PREFETCHWT1
CPUID.(EAX=07H,ECX=0):ECX[0]
Instructions
1 mnemonic
Processors
Knights Landing, Knights Mill

Instructions

Mnemonics with at least one form in PREFETCHWT1. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
PREFETCHWT1Prefetches the cache line of a byte in memory into the second-level cache with intent to write, in exclusive state.1

CPUID and processors

XED splits PREFETCHWT1 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of PREFETCHWT1. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
PREFETCHWT1

PREFETCHWT1
CPUID.(EAX=07H,ECX=0):ECX[0] PREFETCHWT1

Knights Landing, Knights Mill

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.