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Memory, caches and atomics

RAO-INT

Remote atomic operations: atomic add, and, or and xor on memory that return nothing, so the processor may perform them away from the core.

CPUID
RAO_INT
CPUID.(EAX=07H,ECX=1):EAX[3]
Instructions
4 mnemonics
Processors
None announced: XED lists these instructions only under its placeholder for future processors.

RAO-INT (remote atomic operations on integers) adds AADD, AAND, AOR and AXOR: atomic add, and, or and xor on a naturally aligned 32- or 64-bit location in write-back memory, returning nothing and leaving the flags alone. Unlike LOCK ADD, they are weakly ordered, like write-combining stores. Before the operation the processor writes back and invalidates the line in its own cache, and it may write the result only to some levels of the cache hierarchy, which helps with data such as counters that many cores update. Code that needs ordering must add fences.

Intel’s extensions reference lists RAO-INT only for future processors, and XED’s chip model has it only in a placeholder.

Instructions

Mnemonics with at least one form in RAO-INT. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
AADDAtomically adds a register to a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation.2
AANDAtomically ANDs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation.2
AORAtomically ORs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation.2
AXORAtomically XORs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation.2

CPUID and processors

XED splits RAO-INT into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of RAO-INT. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
RAO_INT

RAO_INT
CPUID.(EAX=07H,ECX=1):EAX[3] RAO_INT

None yet: XED lists these instructions only under its placeholder for future processors.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.